On Wed, 02 Nov 2022, "Dixit, Ashutosh" <ashutosh.di...@intel.com> wrote:
> On Fri, 28 Oct 2022 21:42:30 -0700, Gwan-gyeong Mun wrote:
>>
>> Use REG_FIELD_PREP() and a constant value for hwm_field_scale_and_write()
>
> R-b'ing this so that this can get merged since this compile break is
> blocking drm-intel-gt-next pull request:
>
> Reviewed-by: Ashutosh Dixit <ashutosh.di...@intel.com>
Acked-by: Jani Nikula <jani.nik...@intel.com>
on this one as the stopgap measure.
>
>> If the first argument of FIELD_PREP() is not a compile-time constant value
>> or unsigned long long type, this routine of the __BF_FIELD_CHECK() macro
>> used internally by the FIELD_PREP() macro always returns false.
>>
>> BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > \
>> __bf_cast_unsigned(_reg, ~0ull), \
>> _pfx "type of reg too small for mask"); \
>>
>> And it returns a build error by the option among the clang
>> compilation options. [-Werror,-Wtautological-constant-out-of-range-compare]
>>
>> Reported build error while using clang compiler:
>>
>> drivers/gpu/drm/i915/i915_hwmon.c:115:16: error: result of comparison of
>> constant 18446744073709551615 with expression of type 'typeof
>> (_Generic((field_msk), char: (unsigned char)0, unsigned char: (unsigned
>> char)0, signed char: (unsigned char)0, unsigned short: (unsigned short)0,
>> short: (unsigned short)0, unsigned int: (unsigned int)0, int: (unsigned
>> int)0, unsigned long: (unsigned long)0, long: (unsigned long)0, unsigned
>> long long: (unsigned long long)0, long long: (unsigned long long)0, default:
>> (field_msk)))' (aka 'unsigned int') is always false
>> [-Werror,-Wtautological-constant-out-of-range-compare]
>> bits_to_set = FIELD_PREP(field_msk, nval);
>> ^~~~~~~~~~~~~~~~~~~~~~~~~~~
>> ./include/linux/bitfield.h:114:3: note: expanded from macro 'FIELD_PREP'
>> __BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: "); \
>> ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> ./include/linux/bitfield.h:71:53: note: expanded from macro
>> '__BF_FIELD_CHECK'
>> BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > \
>> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~
>> ./include/linux/build_bug.h:39:58: note: expanded from macro
>> 'BUILD_BUG_ON_MSG'
>> ~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~
>> ./include/linux/compiler_types.h:357:22: note: expanded from macro
>> 'compiletime_assert'
>> _compiletime_assert(condition, msg, __compiletime_assert_,
>> __COUNTER__)
>>
>> ~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> ./include/linux/compiler_types.h:345:23: note: expanded from macro
>> '_compiletime_assert'
>> __compiletime_assert(condition, msg, prefix, suffix)
>> ~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> ./include/linux/compiler_types.h:337:9: note: expanded from macro
>> '__compiletime_assert'
>> if (!(condition)) \
>>
>> v2: Use REG_FIELD_PREP() macro instead of FIELD_PREP() (Jani)
>>
>> Fixes: 99f55efb7911 ("drm/i915/hwmon: Power PL1 limit and TDP setting")
>> Cc: Ashutosh Dixit <ashutosh.di...@intel.com>
>> Cc: Anshuman Gupta <anshuman.gu...@intel.com>
>> Cc: Andi Shyti <andi.sh...@linux.intel.com>
>> Cc: Jani Nikula <jani.nik...@intel.com>
>> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong....@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_hwmon.c | 12 +++---------
>> 1 file changed, 3 insertions(+), 9 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_hwmon.c
>> b/drivers/gpu/drm/i915/i915_hwmon.c
>> index 9e9781493025..c588a17f97e9 100644
>> --- a/drivers/gpu/drm/i915/i915_hwmon.c
>> +++ b/drivers/gpu/drm/i915/i915_hwmon.c
>> @@ -101,21 +101,16 @@ hwm_field_read_and_scale(struct hwm_drvdata *ddat,
>> i915_reg_t rgadr,
>>
>> static void
>> hwm_field_scale_and_write(struct hwm_drvdata *ddat, i915_reg_t rgadr,
>> - u32 field_msk, int nshift,
>> - unsigned int scale_factor, long lval)
>> + int nshift, unsigned int scale_factor, long lval)
>> {
>> u32 nval;
>> - u32 bits_to_clear;
>> - u32 bits_to_set;
>>
>> /* Computation in 64-bits to avoid overflow. Round to nearest. */
>> nval = DIV_ROUND_CLOSEST_ULL((u64)lval << nshift, scale_factor);
>>
>> - bits_to_clear = field_msk;
>> - bits_to_set = FIELD_PREP(field_msk, nval);
>> -
>> hwm_locked_with_pm_intel_uncore_rmw(ddat, rgadr,
>> - bits_to_clear, bits_to_set);
>> + PKG_PWR_LIM_1,
>> + REG_FIELD_PREP(PKG_PWR_LIM_1,
>> nval));
>> }
>>
>> /*
>> @@ -406,7 +401,6 @@ hwm_power_write(struct hwm_drvdata *ddat, u32 attr, int
>> chan, long val)
>> case hwmon_power_max:
>> hwm_field_scale_and_write(ddat,
>> hwmon->rg.pkg_rapl_limit,
>> - PKG_PWR_LIM_1,
>> hwmon->scl_shift_power,
>> SF_POWER, val);
>> return 0;
>> --
>> 2.37.1
>>
--
Jani Nikula, Intel Open Source Graphics Center
