[Intel-gfx] [PATCH 4/6] drm/i915/selftests: Run MI_BB perf selftests on SNB

[Ville Syrjala]

From: Ville Syrjälä <ville.syrj...@linux.intel.com>

SNB does have the RING_TIMESTAMP register on the RCS engine.
Run the MI_BB perf tests on it.

Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c 
b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
index 1b75f478d1b8..b11152f87627 100644
--- a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
@@ -125,7 +125,7 @@ static int perf_mi_bb_start(void *arg)
        enum intel_engine_id id;
        int err = 0;
 
-       if (GRAPHICS_VER(gt->i915) < 7) /* for per-engine CS_TIMESTAMP */
+       if (GRAPHICS_VER(gt->i915) < 6) /* for per-engine CS_TIMESTAMP */
                return 0;
 
        perf_begin(gt);
@@ -135,6 +135,9 @@ static int perf_mi_bb_start(void *arg)
                u32 cycles[COUNT];
                int i;
 
+               if (GRAPHICS_VER(engine->i915) < 7 && engine->id != RCS0)
+                       continue;
+
                intel_engine_pm_get(engine);
 
                batch = create_empty_batch(ce);
@@ -249,7 +252,7 @@ static int perf_mi_noop(void *arg)
        enum intel_engine_id id;
        int err = 0;
 
-       if (GRAPHICS_VER(gt->i915) < 7) /* for per-engine CS_TIMESTAMP */
+       if (GRAPHICS_VER(gt->i915) < 6) /* for per-engine CS_TIMESTAMP */
                return 0;
 
        perf_begin(gt);
@@ -259,6 +262,9 @@ static int perf_mi_noop(void *arg)
                u32 cycles[COUNT];
                int i;
 
+               if (GRAPHICS_VER(engine->i915) < 7 && engine->id != RCS0)
+                       continue;
+
                intel_engine_pm_get(engine);
 
                base = create_empty_batch(ce);
-- 
2.37.4