On Tue, Sep 20, 2022 at 01:43:59PM -0700, Matt Atwood wrote:
> Wa_22015475538 applies to all DG2 (and ATSM) skus. The workaround
> implementation is identical to Wa_16011620976. LSC_CHICKEN_BIT_0_UDW is
> a general render register instead of rcs so adding this move to the
> proper wa init function.
>
> bspec:54077
>
> Signed-off-by: Matt Atwood <matthew.s.atw...@intel.com>
Reviewed-by: Matt Roper <matthew.d.ro...@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 11 ++++++++---
> 1 file changed, 8 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 6d2003d598e6..c16e9e3f0d6c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -2108,9 +2108,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
> struct i915_wa_list *wal)
> if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) {
> /* Wa_14013392000:dg2_g11 */
> wa_masked_en(wal, GEN7_ROW_CHICKEN2,
> GEN12_ENABLE_LARGE_GRF_MODE);
> -
> - /* Wa_16011620976:dg2_g11 */
> - wa_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8);
> }
>
> if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
> @@ -2780,6 +2777,14 @@ general_render_compute_wa_init(struct intel_engine_cs
> *engine, struct i915_wa_li
> wa_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB);
> wa_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB);
> }
> +
> + if (IS_DG2(i915)) {
> + /*
> + * Wa_16011620976:dg2_g11
> + * Wa_22015475538:dg2
> + */
> + wa_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8);
> + }
> }
>
> static void
> --
> 2.37.3
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
