On Thu, 08 Sep 2022, Ville Syrjala <ville.syrj...@linux.intel.com> wrote: > From: Ville Syrjälä <ville.syrj...@linux.intel.com> > > Replace the hand rolled stuff with REG_FIELD_GET() for reading > out the skl+ watermark latencies. > > Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nik...@intel.com> > --- > drivers/gpu/drm/i915/display/skl_watermark.c | 22 +++++++------------- > drivers/gpu/drm/i915/i915_reg.h | 8 +++---- > 2 files changed, 12 insertions(+), 18 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c > b/drivers/gpu/drm/i915/display/skl_watermark.c > index 25ca92ae8958..cb297725d5b9 100644 > --- a/drivers/gpu/drm/i915/display/skl_watermark.c > +++ b/drivers/gpu/drm/i915/display/skl_watermark.c > @@ -3239,13 +3239,10 @@ static void skl_read_wm_latency(struct > drm_i915_private *i915, u16 wm[]) > return; > } > > - wm[0] = (val & GEN9_MEM_LATENCY_LEVEL_MASK) * mult; > - wm[1] = ((val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & > - GEN9_MEM_LATENCY_LEVEL_MASK) * mult; > - wm[2] = ((val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & > - GEN9_MEM_LATENCY_LEVEL_MASK) * mult; > - wm[3] = ((val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & > - GEN9_MEM_LATENCY_LEVEL_MASK) * mult; > + wm[0] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_0_4_MASK, val) * mult; > + wm[1] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_1_5_MASK, val) * mult; > + wm[2] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_2_6_MASK, val) * mult; > + wm[3] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_3_7_MASK, val) * mult; > > /* read the second set of memory latencies[4:7] */ > val = 1; /* data0 to be programmed to 1 for second set */ > @@ -3255,13 +3252,10 @@ static void skl_read_wm_latency(struct > drm_i915_private *i915, u16 wm[]) > return; > } > > - wm[4] = (val & GEN9_MEM_LATENCY_LEVEL_MASK) * mult; > - wm[5] = ((val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & > - GEN9_MEM_LATENCY_LEVEL_MASK) * mult; > - wm[6] = ((val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & > - GEN9_MEM_LATENCY_LEVEL_MASK) * mult; > - wm[7] = ((val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & > - GEN9_MEM_LATENCY_LEVEL_MASK) * mult; > + wm[4] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_0_4_MASK, val) * mult; > + wm[5] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_1_5_MASK, val) * mult; > + wm[6] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_2_6_MASK, val) * mult; > + wm[7] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_3_7_MASK, val) * mult; > > adjust_wm_latency(i915, wm, max_level, read_latency); > } > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index c413eec3373f..7289e2b7da2c 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -6551,10 +6551,10 @@ > #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) > #define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18 > #define GEN9_PCODE_READ_MEM_LATENCY 0x6 > -#define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF > -#define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8 > -#define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16 > -#define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24 > +#define GEN9_MEM_LATENCY_LEVEL_3_7_MASK REG_GENMASK(31, 24) > +#define GEN9_MEM_LATENCY_LEVEL_2_6_MASK REG_GENMASK(23, 16) > +#define GEN9_MEM_LATENCY_LEVEL_1_5_MASK REG_GENMASK(15, 8) > +#define GEN9_MEM_LATENCY_LEVEL_0_4_MASK REG_GENMASK(7, 0) > #define SKL_PCODE_LOAD_HDCP_KEYS 0x5 > #define SKL_PCODE_CDCLK_CONTROL 0x7 > #define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3 -- Jani Nikula, Intel Open Source Graphics Center
