From: Dale B Stimson <dale.b.stim...@intel.com>
Some dGfx pcode commands take additional sub-commands and parameters. Add a
couple of helpers to help formatting these commands to improve code
readability.
v2: Fixed commit author (Rodrigo)
v3: Function rename and convert to new uncore interface for pcode functions
Remove unnecessary #define's (Andi)
Cc: Andi Shyti <andi.sh...@intel.com>
Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Signed-off-by: Dale B Stimson <dale.b.stim...@intel.com>
Signed-off-by: Ashutosh Dixit <ashutosh.di...@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.v...@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_pcode.c | 32 ++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_pcode.h | 6 ++++++
3 files changed, 41 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9ccb67eec1bd..5a4689171cc7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6689,6 +6689,9 @@
#define GEN6_PCODE_MAILBOX _MMIO(0x138124)
#define GEN6_PCODE_READY (1 << 31)
+#define GEN6_PCODE_MB_PARAM2 REG_GENMASK(23, 16)
+#define GEN6_PCODE_MB_PARAM1 REG_GENMASK(15, 8)
+#define GEN6_PCODE_MB_COMMAND REG_GENMASK(7, 0)
#define GEN6_PCODE_ERROR_MASK 0xFF
#define GEN6_PCODE_SUCCESS 0x0
#define GEN6_PCODE_ILLEGAL_CMD 0x1
diff --git a/drivers/gpu/drm/i915/intel_pcode.c
b/drivers/gpu/drm/i915/intel_pcode.c
index 66020b2e461f..f80aaf988cea 100644
--- a/drivers/gpu/drm/i915/intel_pcode.c
+++ b/drivers/gpu/drm/i915/intel_pcode.c
@@ -223,3 +223,35 @@ int intel_pcode_init(struct intel_uncore *uncore)
return ret;
}
+
+int intel_pcode_read_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2,
u32 *val)
+{
+ intel_wakeref_t wakeref;
+ u32 mbox;
+ int err;
+
+ mbox = REG_FIELD_PREP(GEN6_PCODE_MB_COMMAND, mbcmd)
+ | REG_FIELD_PREP(GEN6_PCODE_MB_PARAM1, p1)
+ | REG_FIELD_PREP(GEN6_PCODE_MB_PARAM2, p2);
+
+ with_intel_runtime_pm(uncore->rpm, wakeref)
+ err = intel_pcode_read(uncore, mbox, val, NULL);
+
+ return err;
+}
+
+int intel_pcode_write_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32
p2, u32 val)
+{
+ intel_wakeref_t wakeref;
+ u32 mbox;
+ int err;
+
+ mbox = REG_FIELD_PREP(GEN6_PCODE_MB_COMMAND, mbcmd)
+ | REG_FIELD_PREP(GEN6_PCODE_MB_PARAM1, p1)
+ | REG_FIELD_PREP(GEN6_PCODE_MB_PARAM2, p2);
+
+ with_intel_runtime_pm(uncore->rpm, wakeref)
+ err = intel_pcode_write(uncore, mbox, val);
+
+ return err;
+}
diff --git a/drivers/gpu/drm/i915/intel_pcode.h
b/drivers/gpu/drm/i915/intel_pcode.h
index a03d4ef688aa..b0f24bedef92 100644
--- a/drivers/gpu/drm/i915/intel_pcode.h
+++ b/drivers/gpu/drm/i915/intel_pcode.h
@@ -36,4 +36,10 @@ int intel_pcode_request(struct intel_uncore *uncore, u32
mbox, u32 request,
int intel_pcode_init(struct intel_uncore *uncore);
+/*
+ * Helpers for dGfx PCODE mailbox command formatting
+ */
+int intel_pcode_read_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2,
u32 *val);
+int intel_pcode_write_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32
p2, u32 val);
+
#endif /* _INTEL_PCODE_H */
--
2.34.1
