[Intel-gfx] [PATCH] drm/i915/rc6: Access RC6 CTRL regs with forcewake

[Badal Nilawar]

Use forcewake to access RC6 CTRL regs

Signed-off-by: Badal Nilawar <badal.nila...@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_rc6.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c 
b/drivers/gpu/drm/i915/gt/intel_rc6.c
index b4770690e794..acc26b7d2562 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -635,7 +635,7 @@ void intel_rc6_unpark(struct intel_rc6 *rc6)
                return;
 
        /* Restore HW timers for automatic RC6 entry while busy */
-       set(uncore, GEN6_RC_CONTROL, rc6->ctl_enable);
+       intel_uncore_write(uncore, GEN6_RC_CONTROL, rc6->ctl_enable);
 }
 
 void intel_rc6_park(struct intel_rc6 *rc6)
@@ -655,7 +655,7 @@ void intel_rc6_park(struct intel_rc6 *rc6)
                return;
 
        /* Turn off the HW timers and go directly to rc6 */
-       set(uncore, GEN6_RC_CONTROL, GEN6_RC_CTL_RC6_ENABLE);
+       intel_uncore_write(uncore, GEN6_RC_CONTROL, GEN6_RC_CTL_RC6_ENABLE);
 
        if (HAS_RC6pp(rc6_to_i915(rc6)))
                target = 0x6; /* deepest rc6 */
@@ -663,7 +663,7 @@ void intel_rc6_park(struct intel_rc6 *rc6)
                target = 0x5; /* deep rc6 */
        else
                target = 0x4; /* normal rc6 */
-       set(uncore, GEN6_RC_STATE, target << RC_SW_TARGET_STATE_SHIFT);
+       intel_uncore_write(uncore, GEN6_RC_STATE, target << 
RC_SW_TARGET_STATE_SHIFT);
 }
 
 void intel_rc6_disable(struct intel_rc6 *rc6)
-- 
2.25.1