On Wed, Apr 20, 2022 at 10:21:19PM +0300, Imre Deak wrote:
> On Wed, Apr 20, 2022 at 03:09:21PM -0400, Rodrigo Vivi wrote:
> > According to BSPec:
> > Sequence to Allow DC9:
> > 1. Follow Sequence to Disallow DC5.
> >
> > which is:
> > Sequence to Disallow DC5 and DC6
> > Set DC_STATE_EN Dynamic DC State Enable = "Disable".
> >
> > I understand that we haven't had any issue so far. But since
> > DC9 is a software thing, it is better to disable DC5 before
> > to avoid any conflict. And respect the spec to avoid potential
> > future issues.
> >
> > Cc: Imre Deak <imre.d...@intel.com>
> > Cc: Anshuman Gupta <anshuman.gu...@intel.com>
> > Cc: Anusha Srivatsa <anusha.sriva...@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.v...@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display_power.c | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > index 6a5695008f7c..b3cf5182044f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > @@ -883,6 +883,9 @@ static void bxt_enable_dc9(struct drm_i915_private
> > *dev_priv)
> > {
> > assert_can_enable_dc9(dev_priv);
> >
> > + /* Disable DC5 before enabling DC9 */
> > + gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
>
> For DC9 DMC should be disabled already, along with DC states and other
> dependencies like power well 1, etc. That happens in
> bxt/icl_display_core_uninit().
but that wasn't on the suspend_late path... but Anusha is right and
probably the check in the assert is already enough for now... if we
notice that assert is coming we do something else...
I was willing to avoid indirection and the risk of changing something
and this dc5 disable getting forgotten, but with the assert we are
probably good...
let's just ignore this patch...
>
> > +
> > drm_dbg_kms(&dev_priv->drm, "Enabling DC9\n");
> > /*
> > * Power sequencer reset is not needed on
> > --
> > 2.34.1
> >
