[Intel-gfx] [PATCH v2 6/7] drm/i915/dg2: add gsc with special gsc bar offsets

[Daniele Ceraolo Spurio]

From: Tomas Winkler <tomas.wink...@intel.com>

DG2 uses different GSC offsets on memory bar
and uses PXP head (HECI1).

v2 (Daniele): Rebased to before the ATS patches

Signed-off-by: Alexander Usyskin <alexander.usys...@intel.com>
Signed-off-by: Tomas Winkler <tomas.wink...@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> #v1
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gsc.c | 22 +++++++++++++++++++++-
 drivers/gpu/drm/i915/i915_pci.c     |  1 +
 drivers/gpu/drm/i915/i915_reg.h     |  2 ++
 3 files changed, 24 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c 
b/drivers/gpu/drm/i915/gt/intel_gsc.c
index 21e860861f0b5..0e494028b81d0 100644
--- a/drivers/gpu/drm/i915/gt/intel_gsc.c
+++ b/drivers/gpu/drm/i915/gt/intel_gsc.c
@@ -54,6 +54,19 @@ static const struct gsc_def gsc_def_dg1[] = {
        }
 };
 
+static const struct gsc_def gsc_def_dg2[] = {
+       {
+               .name = "mei-gsc",
+               .bar = DG2_GSC_HECI1_BASE,
+               .bar_size = GSC_BAR_LENGTH,
+       },
+       {
+               .name = "mei-gscfi",
+               .bar = DG2_GSC_HECI2_BASE,
+               .bar_size = GSC_BAR_LENGTH,
+       }
+};
+
 static void gsc_release_dev(struct device *dev)
 {
        struct auxiliary_device *aux_dev = to_auxiliary_dev(dev);
@@ -90,7 +103,14 @@ static void gsc_init_one(struct drm_i915_private *i915,
        if (intf_id == 0 && !HAS_HECI_PXP(i915))
                return;
 
-       def = &gsc_def_dg1[intf_id];
+       if (IS_DG1(i915)) {
+               def = &gsc_def_dg1[intf_id];
+       } else if (IS_DG2(i915)) {
+               def = &gsc_def_dg2[intf_id];
+       } else {
+               drm_warn_once(&i915->drm, "Unknown platform\n");
+               return;
+       }
 
        if (!def->name) {
                drm_warn_once(&i915->drm, "HECI%d is not implemented!\n", 
intf_id + 1);
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 06e6dad0d7f71..cb6dcc3f48f4f 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1051,6 +1051,7 @@ static const struct intel_device_info xehpsdv_info = {
        .has_4tile = 1, \
        .has_64k_pages = 1, \
        .has_guc_deprivilege = 1, \
+       .has_heci_pxp = 1, \
        .needs_compact_pt = 1, \
        .platform_engine_mask = \
                BIT(RCS0) | BIT(BCS0) | \
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1dd7b7de60029..efcfe32cd8eba 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -978,6 +978,8 @@
 #define BLT_RING_BASE          0x22000
 #define DG1_GSC_HECI1_BASE     0x00258000
 #define DG1_GSC_HECI2_BASE     0x00259000
+#define DG2_GSC_HECI1_BASE     0x00373000
+#define DG2_GSC_HECI2_BASE     0x00374000
 
 
 
-- 
2.25.1