On Mon, Jan 31, 2022 at 08:29:32PM +0200, Ville Syrjälä wrote:
> On Mon, Jan 31, 2022 at 04:37:00PM +0200, Jani Nikula wrote:
> > > @@ -2508,15 +2509,16 @@ static void i9xx_crtc_enable(struct
> > > intel_atomic_state *state,
> > > const struct intel_crtc_state *new_crtc_state =
> > > intel_atomic_get_new_crtc_state(state, crtc);
> > > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > > + enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
> > > enum pipe pipe = crtc->pipe;
> > >
> > > if (drm_WARN_ON(&dev_priv->drm, crtc->active))
> > > return;
> > >
> > > if (intel_crtc_has_dp_encoder(new_crtc_state)) {
> > > - intel_cpu_transcoder_set_m1_n1(new_crtc_state,
> > > + intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
> > > &new_crtc_state->dp_m_n);
> > > - intel_cpu_transcoder_set_m2_n2(new_crtc_state,
> > > + intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
> >
> > m1_n1 copy paste fail?
>
> Yep. I guess we don't have g4x+DP in CI so this went unnoticed.
And it wouldn't have helped to have one since the introduction of
i9xx_configure_cpu_transcoder() in pathc 9 already fixed this.
So the only way to hit it would have been to bisect through the
series.
--
Ville Syrjälä
Intel
