On Wed, 2022-01-12 at 16:00 +0200, Jouni Högander wrote:
> Now as we have has_psr2_sel_fetch flag we can rely that
> instead of checking each platform separately.
>
> Signed-off-by: Jouni Högander <jouni.hogan...@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 7 -------
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> 2 files changed, 1 insertion(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index a1a663f362e7..c0bf2f6db94e 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -825,13 +825,6 @@ static bool intel_psr2_config_valid(struct intel_dp
> *intel_dp,
> return false;
> }
>
> - /* Wa_16011181250 */
> - if (IS_ROCKETLAKE(dev_priv) || IS_ALDERLAKE_S(dev_priv) ||
> - IS_DG2(dev_priv)) {
> - drm_dbg_kms(&dev_priv->drm, "PSR2 is defeatured for this
> platform\n");
> - return false;
> - }
NACK the both patches.
Those platforms have PSR2 sel fetch but the PSR2 feature was defeatured in
those platforms.
No real product of those platforms will ship with a PSR2 panel so another
reason to not add more stuff to intel_device_info.
Also this change will cause driver to try to enable PSR2 HW tracking in the
platforms above.
> -
> if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
> drm_dbg_kms(&dev_priv->drm, "PSR2 not completely functional in
> this stepping\n");
> return false;
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index beeb42a14aae..d84ca414663c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1502,7 +1502,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr)
> #define HAS_PSR_HW_TRACKING(dev_priv) \
> (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
> -#define HAS_PSR2_SEL_FETCH(dev_priv) (GRAPHICS_VER(dev_priv) >= 12)
> +#define HAS_PSR2_SEL_FETCH(dev_priv)
> (INTEL_INFO(dev_priv)->display.has_psr2_sel_fetch)
> #define HAS_TRANSCODER(dev_priv, trans)
> ((INTEL_INFO(dev_priv)->display.cpu_transcoder_mask & BIT(trans)) != 0)
>
> #define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6)
