For future platforms we'll need to initialize our MMIO function pointers
even earlier. Specifically, we'll need to be able to have register
reads/writes at GTT initialization. Similarly, these platforms also have
MMIO differences based on the PCH id, so while moving stuff around, also
move the PCH initialization.
CC: Chris Wilson <ch...@chris-wilson.co.uk>
Signed-off-by: Ben Widawsky <b...@bwidawsk.net>
---
drivers/gpu/drm/i915/i915_dma.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index ad55c02..df6efbf 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1549,6 +1549,11 @@ int i915_driver_load(struct drm_device *dev, unsigned
long flags)
intel_uncore_early_sanitize(dev);
+ /* This must be called before any calls to HAS_PCH_* */
+ intel_detect_pch(dev);
+
+ intel_uncore_init(dev);
+
ret = i915_gem_gtt_init(dev);
if (ret)
goto out_regs;
@@ -1606,12 +1611,8 @@ int i915_driver_load(struct drm_device *dev, unsigned
long flags)
goto out_mtrrfree;
}
- /* This must be called before any calls to HAS_PCH_* */
- intel_detect_pch(dev);
-
intel_irq_init(dev);
intel_pm_init(dev);
- intel_uncore_init(dev);
intel_uncore_sanitize(dev);
/* Try to make sure MCHBAR is enabled before poking at it */
@@ -1696,6 +1697,7 @@ out_gtt:
drm_mm_takedown(&dev_priv->gtt.base.mm);
dev_priv->gtt.base.cleanup(&dev_priv->gtt.base);
out_regs:
+ intel_uncore_fini(dev);
pci_iounmap(dev->pdev, dev_priv->regs);
put_bridge:
pci_dev_put(dev_priv->bridge_dev);
--
1.8.4
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