[Intel-gfx] [PATCH 1/5] drm/i915/display/adlp: Fix PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR calculation

[José Roberto de Souza]

As the SU_REGION_START begins at 0, the SU_REGION_END should be number
of lines - 1.

BSpec: 50424
Cc: Gwan-gyeong Mun <gwan-gyeong....@intel.com>
Signed-off-by: José Roberto de Souza <jose.so...@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
b/drivers/gpu/drm/i915/display/intel_psr.c
index 3f6fb7d67f84d..36816abb3bcc0 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1501,7 +1501,7 @@ static void psr2_man_trk_ctl_calc(struct intel_crtc_state 
*crtc_state,
 
        if (IS_ALDERLAKE_P(dev_priv)) {
                val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1);
-               val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2);
+               val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 - 1);
        } else {
                drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 || 
clip->y2 % 4);
 
-- 
2.33.0