On Fri, Sep 20, 2013 at 09:35:30AM -0700, Ben Widawsky wrote:
> Future generations will be changing these registers (thanks to design
> for giving us an early heads up). To help abstract, create the
> definition of the base of the register block, and define all registers
> relative to that.
>
> Design has promised to not change the offsets relative to the base.
>
> v2: Also change IS_HASWELL checks to HAS_PSR
>
> CC: Rodrigo Vivi <rodrigo.v...@gmail.com>
Reviewed-by: Rodrigo Vivi <rodrigo.v...@gmail.com>
> CC: Intel GFX <intel-gfx@lists.freedesktop.org>
> Signed-off-by: Ben Widawsky <b...@bwidawsk.net>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 9 +++++----
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 21 +++++++++++----------
> drivers/gpu/drm/i915/intel_dp.c | 21 +++++++++++----------
> 4 files changed, 28 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index aaa46f6..2c32993 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1782,9 +1782,10 @@ static int i915_edp_psr_status(struct seq_file *m,
> void *data)
> struct drm_i915_private *dev_priv = dev->dev_private;
> u32 psrstat, psrperf;
>
> - if (!IS_HASWELL(dev)) {
> + if (!HAS_PSR(dev)) {
> seq_puts(m, "PSR not supported on this platform\n");
> - } else if (IS_HASWELL(dev) && I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE) {
> + } else if (HAS_PSR(dev) &&
> + I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE) {
> seq_puts(m, "PSR enabled\n");
> } else {
> seq_puts(m, "PSR disabled: ");
> @@ -1826,7 +1827,7 @@ static int i915_edp_psr_status(struct seq_file *m, void
> *data)
> return 0;
> }
>
> - psrstat = I915_READ(EDP_PSR_STATUS_CTL);
> + psrstat = I915_READ(EDP_PSR_STATUS_CTL(dev));
>
> seq_puts(m, "PSR Current State: ");
> switch (psrstat & EDP_PSR_STATUS_STATE_MASK) {
> @@ -1898,7 +1899,7 @@ static int i915_edp_psr_status(struct seq_file *m, void
> *data)
> seq_printf(m, "Idle Count: %u\n",
> psrstat & EDP_PSR_STATUS_IDLE_MASK);
>
> - psrperf = (I915_READ(EDP_PSR_PERF_CNT)) & EDP_PSR_PERF_CNT_MASK;
> + psrperf = (I915_READ(EDP_PSR_PERF_CNT(dev))) & EDP_PSR_PERF_CNT_MASK;
> seq_printf(m, "Performance Counter: %u\n", psrperf);
>
> return 0;
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 8f7ca861..c688c38 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1672,6 +1672,7 @@ struct drm_i915_file_private {
> #define HAS_POWER_WELL(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
> !((struct drm_i915_private
> *)dev->dev_private)->is_simulator)
> #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
> +#define HAS_PSR(dev) (IS_HASWELL(dev))
>
> #define INTEL_PCH_DEVICE_ID_MASK 0xff00
> #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 09dd43b..d87c6a3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1870,7 +1870,8 @@
> #define VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B)
>
> /* HSW eDP PSR registers */
> -#define EDP_PSR_CTL 0x64800
> +#define EDP_PSR_BASE(dev) 0x64800
> +#define EDP_PSR_CTL(dev) (EDP_PSR_BASE(dev) + 0)
> #define EDP_PSR_ENABLE (1<<31)
> #define EDP_PSR_LINK_DISABLE (0<<27)
> #define EDP_PSR_LINK_STANDBY (1<<27)
> @@ -1893,16 +1894,16 @@
> #define EDP_PSR_TP1_TIME_0us (3<<4)
> #define EDP_PSR_IDLE_FRAME_SHIFT 0
>
> -#define EDP_PSR_AUX_CTL 0x64810
> -#define EDP_PSR_AUX_DATA1 0x64814
> +#define EDP_PSR_AUX_CTL(dev) (EDP_PSR_BASE(dev) + 0x10)
> +#define EDP_PSR_AUX_DATA1(dev) (EDP_PSR_BASE(dev) +
> 0x14)
> #define EDP_PSR_DPCD_COMMAND 0x80060000
> -#define EDP_PSR_AUX_DATA2 0x64818
> +#define EDP_PSR_AUX_DATA2(dev) (EDP_PSR_BASE(dev) +
> 0x18)
> #define EDP_PSR_DPCD_NORMAL_OPERATION (1<<24)
> -#define EDP_PSR_AUX_DATA3 0x6481c
> -#define EDP_PSR_AUX_DATA4 0x64820
> -#define EDP_PSR_AUX_DATA5 0x64824
> +#define EDP_PSR_AUX_DATA3(dev) (EDP_PSR_BASE(dev) +
> 0x1c)
> +#define EDP_PSR_AUX_DATA4(dev) (EDP_PSR_BASE(dev) +
> 0x20)
> +#define EDP_PSR_AUX_DATA5(dev) (EDP_PSR_BASE(dev) +
> 0x24)
>
> -#define EDP_PSR_STATUS_CTL 0x64840
> +#define EDP_PSR_STATUS_CTL(dev) (EDP_PSR_BASE(dev) +
> 0x40)
> #define EDP_PSR_STATUS_STATE_MASK (7<<29)
> #define EDP_PSR_STATUS_STATE_IDLE (0<<29)
> #define EDP_PSR_STATUS_STATE_SRDONACK (1<<29)
> @@ -1926,10 +1927,10 @@
> #define EDP_PSR_STATUS_SENDING_TP1 (1<<4)
> #define EDP_PSR_STATUS_IDLE_MASK 0xf
>
> -#define EDP_PSR_PERF_CNT 0x64844
> +#define EDP_PSR_PERF_CNT(dev) (EDP_PSR_BASE(dev) + 0x44)
> #define EDP_PSR_PERF_CNT_MASK 0xffffff
>
> -#define EDP_PSR_DEBUG_CTL 0x64860
> +#define EDP_PSR_DEBUG_CTL(dev) (EDP_PSR_BASE(dev) + 0x60)
> #define EDP_PSR_DEBUG_MASK_LPSP (1<<27)
> #define EDP_PSR_DEBUG_MASK_MEMUP (1<<26)
> #define EDP_PSR_DEBUG_MASK_HPD (1<<25)
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index fa5b6da..9ab5271 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1402,10 +1402,10 @@ static bool intel_edp_is_psr_enabled(struct
> drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
>
> - if (!IS_HASWELL(dev))
> + if (!HAS_PSR(dev))
> return false;
>
> - return I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
> + return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
> }
>
> static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
> @@ -1455,7 +1455,7 @@ static void intel_edp_psr_setup(struct intel_dp
> *intel_dp)
> intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
>
> /* Avoid continuous PSR exit by masking memup and hpd */
> - I915_WRITE(EDP_PSR_DEBUG_CTL, EDP_PSR_DEBUG_MASK_MEMUP |
> + I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
> EDP_PSR_DEBUG_MASK_HPD);
>
> intel_dp->psr_setup_done = true;
> @@ -1480,9 +1480,9 @@ static void intel_edp_psr_enable_sink(struct intel_dp
> *intel_dp)
> DP_PSR_MAIN_LINK_ACTIVE);
>
> /* Setup AUX registers */
> - I915_WRITE(EDP_PSR_AUX_DATA1, EDP_PSR_DPCD_COMMAND);
> - I915_WRITE(EDP_PSR_AUX_DATA2, EDP_PSR_DPCD_NORMAL_OPERATION);
> - I915_WRITE(EDP_PSR_AUX_CTL,
> + I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
> + I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
> + I915_WRITE(EDP_PSR_AUX_CTL(dev),
> DP_AUX_CH_CTL_TIME_OUT_400us |
> (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
> (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
> @@ -1505,7 +1505,7 @@ static void intel_edp_psr_enable_source(struct intel_dp
> *intel_dp)
> } else
> val |= EDP_PSR_LINK_DISABLE;
>
> - I915_WRITE(EDP_PSR_CTL, val |
> + I915_WRITE(EDP_PSR_CTL(dev), val |
> EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES |
> max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
> idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
> @@ -1522,7 +1522,7 @@ static bool intel_edp_psr_match_conditions(struct
> intel_dp *intel_dp)
> struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
> struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
>
> - if (!IS_HASWELL(dev)) {
> + if (!HAS_PSR(dev)) {
> DRM_DEBUG_KMS("PSR not supported on this platform\n");
> dev_priv->no_psr_reason = PSR_NO_SOURCE;
> return false;
> @@ -1626,10 +1626,11 @@ void intel_edp_psr_disable(struct intel_dp *intel_dp)
> if (!intel_edp_is_psr_enabled(dev))
> return;
>
> - I915_WRITE(EDP_PSR_CTL, I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE);
> + I915_WRITE(EDP_PSR_CTL(dev),
> + I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
>
> /* Wait till PSR is idle */
> - if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL) &
> + if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
> EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
> DRM_ERROR("Timed out waiting for PSR Idle State\n");
> }
> --
> 1.8.4
>
> _______________________________________________
> Gfx-internal-devel mailing list
> gfx-internal-de...@linux.intel.com
> http://linux.intel.com/mailman/listinfo/gfx-internal-devel
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