On Fri, Jul 23, 2021 at 10:54:07AM -0700, Lucas De Marchi wrote:
> On Fri, Jul 23, 2021 at 10:42:11AM -0700, Matt Roper wrote:
> > From: John Harrison <john.c.harri...@intel.com>
> >
> > Xe_HP can have a lot of extra media engines. This patch adds the basic
> > definitions for them.
> >
> > v2:
> > - Re-order intel_gt_info and intel_device_info slightly to avoid
> > unnecessary padding now that we've increased the size of
> > intel_engine_mask_t. (Tvrtko)
> > v3:
> > - Drop the .hw_id assignments. (Lucas)
> >
> > Cc: Tvrtko Ursulin <tvrtko.ursu...@intel.com>
> > Cc: Lucas De Marchi <lucas.demar...@intel.com>
> > Signed-off-by: John Harrison <john.c.harri...@intel.com>
> > Signed-off-by: Tomas Winkler <tomas.wink...@intel.com>
> > Signed-off-by: Matt Roper <matthew.d.ro...@intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 7 ++--
> > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 44 ++++++++++++++++++++
> > drivers/gpu/drm/i915/gt/intel_engine_types.h | 14 +++++--
> > drivers/gpu/drm/i915/gt/intel_gt_types.h | 5 ++-
> > drivers/gpu/drm/i915/i915_pci.c | 5 ++-
> > drivers/gpu/drm/i915/i915_reg.h | 6 +++
> > drivers/gpu/drm/i915/intel_device_info.h | 3 +-
> > 7 files changed, 71 insertions(+), 13 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > index b29eb9fd0009..461844dffd7e 100644
> > --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > @@ -279,7 +279,7 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32
> > mode)
> > if (mode & EMIT_INVALIDATE)
> > aux_inv = rq->engine->mask & ~BIT(BCS0);
> > if (aux_inv)
> > - cmd += 2 * hweight8(aux_inv) + 2;
> > + cmd += 2 * hweight32(aux_inv) + 2;
> >
> > cs = intel_ring_begin(rq, cmd);
> > if (IS_ERR(cs))
> > @@ -313,9 +313,8 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32
> > mode)
> > struct intel_engine_cs *engine;
> > unsigned int tmp;
> >
> > - *cs++ = MI_LOAD_REGISTER_IMM(hweight8(aux_inv));
> > - for_each_engine_masked(engine, rq->engine->gt,
> > - aux_inv, tmp) {
> > + *cs++ = MI_LOAD_REGISTER_IMM(hweight32(aux_inv));
> > + for_each_engine_masked(engine, rq->engine->gt, aux_inv, tmp) {
> > *cs++ = i915_mmio_reg_offset(aux_inv_reg(engine));
> > *cs++ = AUX_INV;
> > }
> > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > index 4168b9fc59e1..1fc1bd4ad5e3 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > @@ -101,6 +101,34 @@ static const struct engine_info intel_engines[] = {
> > { .graphics_ver = 11, .base = GEN11_BSD4_RING_BASE }
> > },
> > },
> > + [VCS4] = {
> > + .class = VIDEO_DECODE_CLASS,
> > + .instance = 4,
> > + .mmio_bases = {
> > + { .graphics_ver = 11, .base = XEHP_BSD5_RING_BASE }
>
> another thing I raised in my previous review was this ver == 11 here.
> Was this not changed on purpose ?
Woops, looks like I missed that comment in the mix of discussion about
hw_id. I'll respin this one.
Matt
>
> Lucas De Marchi
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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