On 21/07/2021 00:20, Lucas De Marchi wrote:
The engine hw_id is only used by RING_FAULT_REG(), which is not used
since GRAPHICS_VER == 8. We tend to keep adding new defines just to be
consistent, but let's try to remove them and let them defined to 0 when
not used.

Signed-off-by: Lucas De Marchi <lucas.demar...@intel.com>
---
  drivers/gpu/drm/i915/gt/intel_engine_cs.c    | 4 ----
  drivers/gpu/drm/i915/gt/intel_engine_types.h | 4 ----
  2 files changed, 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c 
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index d561573ed98c..a11f69f2e46e 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -80,7 +80,6 @@ static const struct engine_info intel_engines[] = {
                },
        },
        [VCS1] = {
-               .hw_id = VCS1_HW,
                .class = VIDEO_DECODE_CLASS,
                .instance = 1,
                .mmio_bases = {
@@ -89,7 +88,6 @@ static const struct engine_info intel_engines[] = {
                },
        },
        [VCS2] = {
-               .hw_id = VCS2_HW,
                .class = VIDEO_DECODE_CLASS,
                .instance = 2,
                .mmio_bases = {
@@ -97,7 +95,6 @@ static const struct engine_info intel_engines[] = {
                },
        },
        [VCS3] = {
-               .hw_id = VCS3_HW,
                .class = VIDEO_DECODE_CLASS,
                .instance = 3,
                .mmio_bases = {
@@ -114,7 +111,6 @@ static const struct engine_info intel_engines[] = {
                },
        },
        [VECS1] = {
-               .hw_id = VECS1_HW,
                .class = VIDEO_ENHANCEMENT_CLASS,
                .instance = 1,
                .mmio_bases = {
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h 
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 1cb9c3b70b29..a107eb58ffa2 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -34,10 +34,6 @@
  #define VCS0_HW               1
  #define BCS0_HW               2
  #define VECS0_HW      3
-#define VCS1_HW                4
-#define VCS2_HW                6
-#define VCS3_HW                7
-#define VECS1_HW       12
/* Gen11+ HW Engine class + instance */
  #define RENDER_CLASS          0


Story checks out AFAICS.

Reviewed-by: Tvrtko Ursulin <tvrtko.ursu...@intel.com>

Regards,

Tvrtko
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