On Windows, with the hang bit set, we do the cache line replacement after an error occurs, but nothing else [so L3 log registers are definitely responsive, I don't know if other memory is also].
-----Original Message----- From: daniel.vet...@ffwll.ch [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel Vetter Sent: Tuesday, September 17, 2013 12:28 AM To: Widawsky, Benjamin Cc: Bell, Bryan J; intel-gfx@lists.freedesktop.org; Venkatesh, Vishnu Subject: Re: [Intel-gfx] [PATCH 0/8] DPF (GPU l3 parity detection) improvements On Tue, Sep 17, 2013 at 6:15 AM, Ben Widawsky <benjamin.widaw...@intel.com> wrote: > I see. I had thought the hang bit was part of the test injection, when > it's actually modifying the behavior or L3 errors. Any opinions on > what the default should be (agreed that policy should be controlled by > user space, but we can control the default)? What does a "hang" mean > exactly, is the rest of memory still responsive, L3? I guess we want a hang-on-L3-error bit at context creation. But that seems orthogonal to fixing l3 error reporting on hsw and wiring up the test facilities, so I'd wait until someone screams for this. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
