From: Ville Syrjälä <ville.syrj...@linux.intel.com>
Just add the 120MHz reference clock case, and magically the
function appears to be ready to for PCH DPLLs.
Now, 120MHz might not always be correct, but we're already using
hardocoded values for other platforms, so the situation isn't
getting much worse.
Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 754de85..d89ea94 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7372,7 +7372,9 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
return;
}
- if (IS_PINEVIEW(dev))
+ if (HAS_PCH_SPLIT(dev))
+ i9xx_clock(120000, &clock);
+ else if (IS_PINEVIEW(dev))
pineview_clock(96000, &clock);
else
i9xx_clock(96000, &clock);
--
1.8.1.5
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