> -----Original Message-----
> From: Roper, Matthew D <matthew.d.ro...@intel.com>
> Sent: Saturday, May 15, 2021 8:40 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Mun, Gwan-gyeong <gwan-gyeong....@intel.com>; Ville Syrjälä
> <ville.syrj...@linux.intel.com>; Souza, Jose <jose.so...@intel.com>; Gupta,
> Anshuman <anshuman.gu...@intel.com>; Roper, Matthew D
> <matthew.d.ro...@intel.com>
> Subject: [PATCH v4 15/23] drm/i915/display: Replace dc3co_enabled with
> dc3co_exitline on intel_psr struct
>
> From: Gwan-gyeong Mun <gwan-gyeong....@intel.com>
>
> It replaces dc3co_enabled with dc3co_exitline on intel_psr struct. And it
> saves
> dc3co_exitline, not dc3co_enabled, so we can use dc3co_exitline without
> intel_crtc_state on other psr internal function like as
> intel_psr_enable_source().
>
> Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
> Cc: José Roberto de Souza <jose.so...@intel.com>
> Cc: Anshuman Gupta <anshuman.gu...@intel.com>
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong....@intel.com>
> Signed-off-by: Matt Roper <matthew.d.ro...@intel.com>
Looks good to me.
Reviewed-by: Anshuman Gupta <anshuman.gu...@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display_types.h | 2 +-
> drivers/gpu/drm/i915/display/intel_psr.c | 10 +++++-----
> 2 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 9e9f768e2d7f..b8d1f702d808 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1498,7 +1498,7 @@ struct intel_psr {
> bool sink_not_reliable;
> bool irq_aux_error;
> u16 su_x_granularity;
> - bool dc3co_enabled;
> + u32 dc3co_exitline;
> u32 dc3co_exit_delay;
> struct delayed_work dc3co_work;
> struct drm_dp_vsc_sdp vsc;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index acaf3d459821..5bafd0de6ad9 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -638,7 +638,7 @@ static void tgl_dc3co_disable_work(struct work_struct
> *work)
>
> static void tgl_disallow_dc3co_on_psr2_exit(struct intel_dp *intel_dp) {
> - if (!intel_dp->psr.dc3co_enabled)
> + if (!intel_dp->psr.dc3co_exitline)
> return;
>
> cancel_delayed_work(&intel_dp->psr.dc3co_work);
> @@ -1010,7 +1010,7 @@ static void intel_psr_enable_source(struct intel_dp
> *intel_dp,
>
> psr_irq_control(intel_dp);
>
> - if (crtc_state->dc3co_exitline) {
> + if (intel_dp->psr.dc3co_exitline) {
> u32 val;
>
> /*
> @@ -1019,7 +1019,7 @@ static void intel_psr_enable_source(struct intel_dp
> *intel_dp,
> */
> val = intel_de_read(dev_priv, EXITLINE(cpu_transcoder));
> val &= ~EXITLINE_MASK;
> - val |= crtc_state->dc3co_exitline << EXITLINE_SHIFT;
> + val |= intel_dp->psr.dc3co_exitline << EXITLINE_SHIFT;
> val |= EXITLINE_ENABLE;
> intel_de_write(dev_priv, EXITLINE(cpu_transcoder), val);
> }
> @@ -1044,11 +1044,11 @@ static void intel_psr_enable_locked(struct intel_dp
> *intel_dp,
> intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
> intel_dp->psr.busy_frontbuffer_bits = 0;
> intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
> - intel_dp->psr.dc3co_enabled = !!crtc_state->dc3co_exitline;
> intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
> /* DC5/DC6 requires at least 6 idle frames */
> val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6);
> intel_dp->psr.dc3co_exit_delay = val;
> + intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline;
> intel_dp->psr.psr2_sel_fetch_enabled = crtc_state-
> >enable_psr2_sel_fetch;
>
> /*
> @@ -1818,7 +1818,7 @@ tgl_dc3co_flush(struct intel_dp *intel_dp, unsigned
> int frontbuffer_bits, {
> mutex_lock(&intel_dp->psr.lock);
>
> - if (!intel_dp->psr.dc3co_enabled)
> + if (!intel_dp->psr.dc3co_exitline)
> goto unlock;
>
> if (!intel_dp->psr.psr2_enabled || !intel_dp->psr.active)
> --
> 2.25.4
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