On Tue, 04 May 2021, Ville Syrjala <ville.syrj...@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrj...@linux.intel.com>
>
> For some reason the dg1 buf trans tables have been stuffed into
> icl_get_combo_buf_trans_edp() which doesn't even get called
> on dg1. Split them out into a proper dg1 specific function,
> and also make sure we use the proper buf trans tables for
> DP as well as eDP.
>
> v2: Add the hobl stuff
>
> Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nik...@intel.com>
> ---
> .../drm/i915/display/intel_ddi_buf_trans.c | 55 +++++++++++++++++--
> 1 file changed, 49 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> index fd55c812f14a..7a1dbf5281cb 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> @@ -1286,12 +1286,6 @@ icl_get_combo_buf_trans_edp(struct intel_encoder
> *encoder,
> } else if (dev_priv->vbt.edp.low_vswing) {
> return
> intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2,
> n_entries);
> - } else if (IS_DG1(dev_priv) && crtc_state->port_clock > 270000) {
> - return
> intel_get_buf_trans(&dg1_combo_phy_ddi_translations_dp_hbr2_hbr3,
> - n_entries);
> - } else if (IS_DG1(dev_priv)) {
> - return
> intel_get_buf_trans(&dg1_combo_phy_ddi_translations_dp_rbr_hbr,
> - n_entries);
> }
>
> return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
> @@ -1506,6 +1500,53 @@ tgl_get_combo_buf_trans(struct intel_encoder *encoder,
> return tgl_get_combo_buf_trans_dp(encoder, crtc_state,
> n_entries);
> }
>
> +static const struct intel_ddi_buf_trans *
> +dg1_get_combo_buf_trans_dp(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state,
> + int *n_entries)
> +{
> + if (crtc_state->port_clock > 270000)
> + return
> intel_get_buf_trans(&dg1_combo_phy_ddi_translations_dp_hbr2_hbr3,
> + n_entries);
> + else
> + return
> intel_get_buf_trans(&dg1_combo_phy_ddi_translations_dp_rbr_hbr,
> + n_entries);
> +}
> +
> +static const struct intel_ddi_buf_trans *
> +dg1_get_combo_buf_trans_edp(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state,
> + int *n_entries)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +
> + if (crtc_state->port_clock > 540000)
> + return
> intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr3,
> + n_entries);
> + else if (dev_priv->vbt.edp.hobl && !intel_dp->hobl_failed)
> + return
> intel_get_buf_trans(&tgl_combo_phy_ddi_translations_edp_hbr2_hobl,
> + n_entries);
> + else if (dev_priv->vbt.edp.low_vswing)
> + return
> intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2,
> + n_entries);
> + else
> + return dg1_get_combo_buf_trans_dp(encoder, crtc_state,
> n_entries);
> +}
> +
> +static const struct intel_ddi_buf_trans *
> +dg1_get_combo_buf_trans(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state,
> + int *n_entries)
> +{
> + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> + return icl_get_combo_buf_trans_hdmi(encoder, crtc_state,
> n_entries);
> + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
> + return dg1_get_combo_buf_trans_edp(encoder, crtc_state,
> n_entries);
> + else
> + return dg1_get_combo_buf_trans_dp(encoder, crtc_state,
> n_entries);
> +}
> +
> static const struct intel_ddi_buf_trans *
> rkl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state,
> @@ -1614,6 +1655,8 @@ void intel_ddi_buf_trans_init(struct intel_encoder
> *encoder)
>
> if (IS_ROCKETLAKE(i915)) {
> encoder->get_buf_trans = rkl_get_combo_buf_trans;
> + } else if (IS_DG1(i915)) {
> + encoder->get_buf_trans = dg1_get_combo_buf_trans;
> } else if (DISPLAY_VER(i915) >= 12) {
> if (intel_phy_is_combo(i915, phy))
> encoder->get_buf_trans = tgl_get_combo_buf_trans;
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
