On Sat, Apr 17, 2021 at 05:21:24PM -0700, José Roberto de Souza wrote:
> No functional changes in here.
>
> Cc: Matt Atwood <matthew.s.atw...@intel.com>
Reviewed-by: Radhakrishna Sripada <radhakrishna.srip...@intel.com>
> Signed-off-by: José Roberto de Souza <jose.so...@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 17 ++++++-----------
> 1 file changed, 6 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 72bcc10cae4f..cf380f98d54c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2865,24 +2865,19 @@ void intel_dp_set_infoframes(struct intel_encoder
> *encoder,
> u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
> VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
> VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
> - u32 val = intel_de_read(dev_priv, reg);
> + u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
>
> /* TODO: Add DSC case (DIP_ENABLE_PPS) */
> /* When PSR is enabled, this routine doesn't disable VSC DIP */
> - if (crtc_state->has_psr)
> - val &= ~dip_enable;
> - else
> - val &= ~(dip_enable | VIDEO_DIP_ENABLE_VSC_HSW);
> -
> - if (!enable) {
> - intel_de_write(dev_priv, reg, val);
> - intel_de_posting_read(dev_priv, reg);
> - return;
> - }
> + if (!crtc_state->has_psr)
> + val &= ~VIDEO_DIP_ENABLE_VSC_HSW;
>
> intel_de_write(dev_priv, reg, val);
> intel_de_posting_read(dev_priv, reg);
>
> + if (!enable)
> + return;
> +
> /* When PSR is enabled, VSC SDP is handled by PSR routine */
> if (!crtc_state->has_psr)
> intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
> --
> 2.31.1
>
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