On Mon, Mar 22, 2021 at 01:58:04PM -0700, José Roberto de Souza wrote:
> Power wells are only part of display block and not necessary when
> running a headless driver.
>
> Cc: Lucas De Marchi <lucas.demar...@intel.com>
Reviewed-by: Radhakrishna Sripada <radhakrishna.srip...@intel.com>
> Signed-off-by: José Roberto de Souza <jose.so...@intel.com>
> Signed-off-by: Jani Nikula <jani.nik...@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display_power.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 7e0eaa872350..e6a3b3e6b1f7 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -4673,7 +4673,10 @@ int intel_power_domains_init(struct drm_i915_private
> *dev_priv)
> * The enabling order will be from lower to higher indexed wells,
> * the disabling order is reversed.
> */
> - if (IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv)) {
> + if (!HAS_DISPLAY(dev_priv)) {
> + power_domains->power_well_count = 0;
> + err = 0;
> + } else if (IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv)) {
> err = set_power_wells_mask(power_domains, tgl_power_wells,
> BIT_ULL(TGL_DISP_PW_TC_COLD_OFF));
> } else if (IS_ROCKETLAKE(dev_priv)) {
> --
> 2.31.0
>
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