On Wed, Jan 13, 2021 at 02:09:20PM -0800, Manasi Navare wrote:
> From: Ville Syrjälä <ville.syrj...@linux.intel.com>
>
> The vrr calculations will need to know the framestart delay value
> we use. Currently we program it always to zero, but should that change
> we probably want to stash it somewhere.
>
> Could stick it into the crtc_state I suppose, but since we never
> change it let's just stuff it into dev_priv for now.
>
> Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 22 +++++++++++---------
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> 2 files changed, 14 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 0189d379a55e..67a55cfa5354 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1610,7 +1610,7 @@ static void ilk_enable_pch_transcoder(const struct
> intel_crtc_state *crtc_state)
> val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
> /* Configure frame start delay to match the CPU */
> val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
> - val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
> + val |=
> TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->framestart_delay);
> intel_de_write(dev_priv, reg, val);
> }
>
> @@ -1621,7 +1621,7 @@ static void ilk_enable_pch_transcoder(const struct
> intel_crtc_state *crtc_state)
> if (HAS_PCH_IBX(dev_priv)) {
> /* Configure frame start delay to match the CPU */
> val &= ~TRANS_FRAME_START_DELAY_MASK;
> - val |= TRANS_FRAME_START_DELAY(0);
> + val |= TRANS_FRAME_START_DELAY(dev_priv->framestart_delay);
>
> /*
> * Make the BPC in transcoder be consistent with
> @@ -1666,7 +1666,7 @@ static void lpt_enable_pch_transcoder(struct
> drm_i915_private *dev_priv,
> val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
> /* Configure frame start delay to match the CPU */
> val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
> - val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
> + val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->framestart_delay);
> intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
>
> val = TRANS_ENABLE;
> @@ -6679,7 +6679,7 @@ static void hsw_set_frame_start_delay(const struct
> intel_crtc_state *crtc_state)
>
> val = intel_de_read(dev_priv, reg);
> val &= ~HSW_FRAME_START_DELAY_MASK;
> - val |= HSW_FRAME_START_DELAY(0);
> + val |= HSW_FRAME_START_DELAY(dev_priv->framestart_delay);
> intel_de_write(dev_priv, reg, val);
> }
>
> @@ -8741,7 +8741,7 @@ static void i9xx_set_pipeconf(const struct
> intel_crtc_state *crtc_state)
>
> pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
>
> - pipeconf |= PIPECONF_FRAME_START_DELAY(0);
> + pipeconf |= PIPECONF_FRAME_START_DELAY(dev_priv->framestart_delay);
>
> intel_de_write(dev_priv, PIPECONF(crtc->pipe), pipeconf);
> intel_de_posting_read(dev_priv, PIPECONF(crtc->pipe));
> @@ -9850,7 +9850,7 @@ static void ilk_set_pipeconf(const struct
> intel_crtc_state *crtc_state)
>
> val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
>
> - val |= PIPECONF_FRAME_START_DELAY(0);
> + val |= PIPECONF_FRAME_START_DELAY(dev_priv->framestart_delay);
>
> intel_de_write(dev_priv, PIPECONF(pipe), val);
> intel_de_posting_read(dev_priv, PIPECONF(pipe));
> @@ -17153,6 +17153,8 @@ int intel_modeset_init_noirq(struct drm_i915_private
> *i915)
> i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI |
> WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
>
> + i915->framestart_delay = 0; /* 0-3 */
Should we change this to default to 1 and then since its 0 based use
framestart_delay - 1 everywhere?
Manasi
> +
> intel_mode_config_init(i915);
>
> ret = intel_cdclk_init(i915);
> @@ -17487,7 +17489,7 @@ static void intel_sanitize_frame_start_delay(const
> struct intel_crtc_state *crtc
>
> val = intel_de_read(dev_priv, reg);
> val &= ~HSW_FRAME_START_DELAY_MASK;
> - val |= HSW_FRAME_START_DELAY(0);
> + val |= HSW_FRAME_START_DELAY(dev_priv->framestart_delay);
> intel_de_write(dev_priv, reg, val);
> } else {
> i915_reg_t reg = PIPECONF(cpu_transcoder);
> @@ -17495,7 +17497,7 @@ static void intel_sanitize_frame_start_delay(const
> struct intel_crtc_state *crtc
>
> val = intel_de_read(dev_priv, reg);
> val &= ~PIPECONF_FRAME_START_DELAY_MASK;
> - val |= PIPECONF_FRAME_START_DELAY(0);
> + val |= PIPECONF_FRAME_START_DELAY(dev_priv->framestart_delay);
> intel_de_write(dev_priv, reg, val);
> }
>
> @@ -17508,7 +17510,7 @@ static void intel_sanitize_frame_start_delay(const
> struct intel_crtc_state *crtc
>
> val = intel_de_read(dev_priv, reg);
> val &= ~TRANS_FRAME_START_DELAY_MASK;
> - val |= TRANS_FRAME_START_DELAY(0);
> + val |= TRANS_FRAME_START_DELAY(dev_priv->framestart_delay);
> intel_de_write(dev_priv, reg, val);
> } else {
> enum pipe pch_transcoder = intel_crtc_pch_transcoder(crtc);
> @@ -17517,7 +17519,7 @@ static void intel_sanitize_frame_start_delay(const
> struct intel_crtc_state *crtc
>
> val = intel_de_read(dev_priv, reg);
> val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
> - val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
> + val |=
> TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->framestart_delay);
> intel_de_write(dev_priv, reg, val);
> }
> }
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 15e016194685..94a27e72b0a8 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1182,6 +1182,8 @@ struct drm_i915_private {
> struct file *mmap_singleton;
> } gem;
>
> + u8 framestart_delay;
> +
> u8 pch_ssc_use;
>
> /* For i915gm/i945gm vblank irq workaround */
> --
> 2.19.1
>
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