Before we clear any state that may be being written by an interrupt
handler on another core, flush the interrupt handlers.
Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index b31ce0d60028..e8c20f80e353 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2656,7 +2656,10 @@ static void enable_error_interrupt(struct
intel_engine_cs *engine)
{
u32 status;
+ /* Flush ongoing GT interrupts before touching interrupt state */
+ synchronize_hardirq(engine->i915->drm.irq);
engine->execlists.error_interrupt = 0;
+
ENGINE_WRITE(engine, RING_EMR, ~0u);
ENGINE_WRITE(engine, RING_EIR, ~0u); /* clear all existing errors */
--
2.20.1
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