Reviewed-by: Rodrigo Vivi <rodrigo.v...@gmail.com>
Thanks for pointing me the doc that explains why 800 MHz when using FCLK input.
;)
On Tue, Aug 06, 2013 at 06:57:11PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zan...@intel.com>
>
> We already have code to disable LCPLL and switch to FCLK, so we need this too.
> We still don't call the code to disable LCPLL, but we'll call it when we add
> support for Package C8+.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zan...@intel.com>
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 9 ++++++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index b8c096b..63aca49 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1139,10 +1139,13 @@ static void intel_disable_ddi(struct intel_encoder
> *intel_encoder)
>
> int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
> {
> - if (I915_READ(HSW_FUSE_STRAP) & HSW_CDCLK_LIMIT)
> + uint32_t lcpll = I915_READ(LCPLL_CTL);
> +
> + if (lcpll & LCPLL_CD_SOURCE_FCLK)
> + return 800000;
> + else if (I915_READ(HSW_FUSE_STRAP) & HSW_CDCLK_LIMIT)
> return 450000;
> - else if ((I915_READ(LCPLL_CTL) & LCPLL_CLK_FREQ_MASK) ==
> - LCPLL_CLK_FREQ_450)
> + else if ((lcpll & LCPLL_CLK_FREQ_MASK) == LCPLL_CLK_FREQ_450)
> return 450000;
> else if (IS_ULT(dev_priv->dev))
> return 337500;
> --
> 1.8.1.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
