For the PTEs we get an LM bit, to signal whether the page resides in
SMEM or LMEM.

Signed-off-by: Matthew Auld <matthew.a...@intel.com>
Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com>
Cc: Abdiel Janulgue <abdiel.janul...@linux.intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathap...@intel.com>
Signed-off-by: Venkata Sandeep Dhanalakota <venkata.s.dhanalak...@intel.com>
---
 drivers/gpu/drm/i915/gt/gen8_ppgtt.c  | 35 ++++++++++++++++++++++-----
 drivers/gpu/drm/i915/gt/intel_gtt.h   |  3 +++
 drivers/gpu/drm/i915/gt/intel_ppgtt.c |  4 +++
 3 files changed, 36 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c 
b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index e2f1dfc48d43..b6fcebeef02a 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -5,6 +5,7 @@
 
 #include <linux/log2.h>
 
+#include "gem/i915_gem_lmem.h"
 #include "gen8_ppgtt.h"
 #include "i915_scatterlist.h"
 #include "i915_trace.h"
@@ -50,6 +51,21 @@ static u64 gen8_pte_encode(dma_addr_t addr,
        return pte;
 }
 
+static u64 gen12_pte_encode(dma_addr_t addr,
+                           enum i915_cache_level level,
+                           u32 flags)
+{
+       gen8_pte_t pte = addr | _PAGE_PRESENT | _PAGE_RW;
+
+       if (unlikely(flags & PTE_READ_ONLY))
+               pte &= ~_PAGE_RW;
+
+       if (flags & PTE_LM)
+               pte |= GEN12_PPGTT_PTE_LM;
+
+       return pte;
+}
+
 static void gen8_ppgtt_notify_vgt(struct i915_ppgtt *ppgtt, bool create)
 {
        struct drm_i915_private *i915 = ppgtt->vm.i915;
@@ -365,7 +381,7 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt,
                      u32 flags)
 {
        struct i915_page_directory *pd;
-       const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, flags);
+       const gen8_pte_t pte_encode = ppgtt->vm.pte_encode(0, cache_level, 
flags);
        gen8_pte_t *vaddr;
        bool needs_flush;
 
@@ -413,7 +429,7 @@ static void gen8_ppgtt_insert_huge(struct i915_vma *vma,
                                   enum i915_cache_level cache_level,
                                   u32 flags)
 {
-       const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, flags);
+       const gen8_pte_t pte_encode = vma->vm->pte_encode(0, cache_level, 
flags);
        unsigned int rem = sg_dma_len(iter->sg);
        u64 start = vma->node.start;
        bool needs_flush;
@@ -558,6 +574,7 @@ static void gen8_ppgtt_insert(struct i915_address_space *vm,
 
 static int gen8_init_scratch(struct i915_address_space *vm)
 {
+       u32 pte_flags = vm->has_read_only;
        int ret;
        int i;
 
@@ -581,9 +598,12 @@ static int gen8_init_scratch(struct i915_address_space *vm)
        if (ret)
                return ret;
 
+       if (i915_gem_object_is_lmem(vm->scratch[0]))
+               pte_flags |= PTE_LM;
+
        vm->scratch[0]->encode =
-               gen8_pte_encode(px_dma(vm->scratch[0]),
-                               I915_CACHE_LLC, vm->has_read_only);
+               vm->pte_encode(px_dma(vm->scratch[0]),
+                              I915_CACHE_LLC, pte_flags);
 
        for (i = 1; i <= vm->top; i++) {
                struct drm_i915_gem_object *obj;
@@ -713,6 +733,11 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt)
        else
                ppgtt->vm.alloc_pt_dma = alloc_pt_dma;
 
+       if (INTEL_GEN(gt->i915) >= 12)
+               ppgtt->vm.pte_encode = gen12_pte_encode;
+       else
+               ppgtt->vm.pte_encode = gen8_pte_encode;
+
        err = gen8_init_scratch(&ppgtt->vm);
        if (err)
                goto err_free;
@@ -734,8 +759,6 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt)
        ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc;
        ppgtt->vm.clear_range = gen8_ppgtt_clear;
 
-       ppgtt->vm.pte_encode = gen8_pte_encode;
-
        if (intel_vgpu_active(gt->i915))
                gen8_ppgtt_notify_vgt(ppgtt, true);
 
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h 
b/drivers/gpu/drm/i915/gt/intel_gtt.h
index d96bd19d1b47..f47899ef36f4 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -85,6 +85,8 @@ typedef u64 gen8_pte_t;
 #define BYT_PTE_SNOOPED_BY_CPU_CACHES  REG_BIT(2)
 #define BYT_PTE_WRITEABLE              REG_BIT(1)
 
+#define GEN12_PPGTT_PTE_LM (1 << 11)
+
 /*
  * Cacheability Control is a 4-bit value. The low three bits are stored in bits
  * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.
@@ -268,6 +270,7 @@ struct i915_address_space {
                          enum i915_cache_level level,
                          u32 flags); /* Create a valid PTE */
 #define PTE_READ_ONLY  BIT(0)
+#define PTE_LM          BIT(1)
 
        void (*allocate_va_range)(struct i915_address_space *vm,
                                  struct i915_vm_pt_stash *stash,
diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c 
b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
index 2d74ae950e4b..731d8730fa5f 100644
--- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
@@ -7,6 +7,8 @@
 
 #include "i915_trace.h"
 #include "intel_gtt.h"
+#include "gem/i915_gem_lmem.h"
+#include "gem/i915_gem_region.h"
 #include "gen6_ppgtt.h"
 #include "gen8_ppgtt.h"
 
@@ -193,6 +195,8 @@ void ppgtt_bind_vma(struct i915_address_space *vm,
        pte_flags = 0;
        if (i915_gem_object_is_readonly(vma->obj))
                pte_flags |= PTE_READ_ONLY;
+       if (i915_gem_object_is_lmem(vma->obj))
+               pte_flags |= PTE_LM;
 
        vm->insert_entries(vm, vma, cache_level, pte_flags);
        wmb();
-- 
2.26.2

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