Platforms with South Display Engine on PCH, doesn't
require to get/put the AUX power domain in order to
access PPS register because PPS registers are always on
with South display on PCH.
Cc: Imre Deak <imre.d...@intel.com>
Cc: <sta...@vger.kernel.org>
Signed-off-by: Anshuman Gupta <anshuman.gu...@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 13 ++++++++-----
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 3896d08c4177..84a2c49e154c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -872,8 +872,9 @@ pps_lock(struct intel_dp *intel_dp)
* See intel_power_sequencer_reset() why we need
* a power domain reference here.
*/
- wakeref = intel_display_power_get(dev_priv,
-
intel_aux_power_domain(dp_to_dig_port(intel_dp)));
+ if (!HAS_PCH_SPLIT(dev_priv))
+ wakeref = intel_display_power_get(dev_priv,
+
intel_aux_power_domain(dp_to_dig_port(intel_dp)));
mutex_lock(&dev_priv->pps_mutex);
@@ -886,9 +887,11 @@ pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t
wakeref)
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
mutex_unlock(&dev_priv->pps_mutex);
- intel_display_power_put(dev_priv,
-
intel_aux_power_domain(dp_to_dig_port(intel_dp)),
- wakeref);
+
+ if (!HAS_PCH_SPLIT(dev_priv))
+ intel_display_power_put(dev_priv,
+
intel_aux_power_domain(dp_to_dig_port(intel_dp)),
+ wakeref);
return 0;
}
--
2.26.2
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