On Wed, Oct 21, 2020 at 06:31:56AM -0700, Aditya Swarup wrote:
> From: Caz Yokoyama <caz.yokoy...@intel.com>
>
> - Add the initial platform information for Alderlake-S.
> - Specify ppgtt_size value
> - Add dma_mask_size
> - Add ADLS REVIDs
> - HW tracking(Selective Update Tracking Enable) has been removed from
> ADLS. Disable PSR2 till we enable software/manual tracking.
>
> Bspec: 53597
> Bspec: 53648
> Bspec: 53655
> Bspec: 48028
> Bspec: 53650
> BSpec: 50422
>
> Cc: José Roberto de Souza <jose.so...@intel.com>
> Cc: Matt Roper <matthew.d.ro...@intel.com>
> Cc: Lucas De Marchi <lucas.demar...@intel.com>
> Cc: Anusha Srivatsa <anusha.sriva...@intel.com>
> Cc: Jani Nikula <jani.nik...@intel.com>
> Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
> Cc: Imre Deak <imre.d...@intel.com>
> Signed-off-by: Caz Yokoyama <caz.yokoy...@intel.com>
> Signed-off-by: Aditya Swarup <aditya.swa...@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 9 +++++++++
> drivers/gpu/drm/i915/i915_pci.c | 12 ++++++++++++
> drivers/gpu/drm/i915/intel_device_info.c | 1 +
> drivers/gpu/drm/i915/intel_device_info.h | 1 +
> include/drm/i915_pciids.h | 13 +++++++++++++
> 5 files changed, 36 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index bcd8650603d8..4fea3d5e01f4 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1424,6 +1424,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
> #define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
> #define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG1)
> +#define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)
> #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
> (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
> #define IS_BDW_ULT(dev_priv) \
> @@ -1613,6 +1614,14 @@ tgl_revids_get(struct drm_i915_private *dev_priv)
> #define IS_DG1_REVID(p, since, until) \
> (IS_DG1(p) && IS_REVID(p, since, until))
>
> +#define ADLS_REVID_A0 0x0
> +#define ADLS_REVID_B0 0x4
> +#define ADLS_REVID_C0 0x8
> +#define ADLS_REVID_D0 0xC
> +
> +#define IS_ADLS_REVID(p, since, until) \
> + (IS_ALDERLAKE_S(p) && IS_REVID(p, since, until))
Based on bspec 53655 it doesn't look like it's this simple anymore; the
display stepping and gfx/media stepping aren't the same for a given
revid. We'll need to do something like we have on TGL and have a table
that maps them for use with IS_ADLS_GT_REVID() and IS_ADLS_DISP_REVID().
Matt
> +
> #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
> #define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
> #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 27964ac0638a..d39a7389b305 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -924,6 +924,17 @@ static const struct intel_device_info dg1_info
> __maybe_unused = {
> .ppgtt_size = 47,
> };
>
> +static const struct intel_device_info adl_s_info = {
> + GEN12_FEATURES,
> + PLATFORM(INTEL_ALDERLAKE_S),
> + .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
> + .require_force_probe = 1,
> + .display.has_psr_hw_tracking = 0,
> + .platform_engine_mask =
> + BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
> + .dma_mask_size = 46,
> +};
> +
> #undef GEN
> #undef PLATFORM
>
> @@ -1000,6 +1011,7 @@ static const struct pci_device_id pciidlist[] = {
> INTEL_JSL_IDS(&jsl_info),
> INTEL_TGL_12_IDS(&tgl_info),
> INTEL_RKL_IDS(&rkl_info),
> + INTEL_ADLS_IDS(&adl_s_info),
> {0, 0, 0}
> };
> MODULE_DEVICE_TABLE(pci, pciidlist);
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> b/drivers/gpu/drm/i915/intel_device_info.c
> index e67cec8fa2aa..7310e019c611 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -66,6 +66,7 @@ static const char * const platform_names[] = {
> PLATFORM_NAME(TIGERLAKE),
> PLATFORM_NAME(ROCKETLAKE),
> PLATFORM_NAME(DG1),
> + PLATFORM_NAME(ALDERLAKE_S),
> };
> #undef PLATFORM_NAME
>
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> b/drivers/gpu/drm/i915/intel_device_info.h
> index d92fa041c700..360f3f1835f5 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -84,6 +84,7 @@ enum intel_platform {
> INTEL_TIGERLAKE,
> INTEL_ROCKETLAKE,
> INTEL_DG1,
> + INTEL_ALDERLAKE_S,
> INTEL_MAX_PLATFORMS
> };
>
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index 3b5ed1e4f3ec..9a0d58524cb1 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -635,4 +635,17 @@
> INTEL_VGA_DEVICE(0x4907, info), \
> INTEL_VGA_DEVICE(0x4908, info)
>
> +/* ADL-S */
> +#define INTEL_ADLS_IDS(info) \
> + INTEL_VGA_DEVICE(0x4680, info), \
> + INTEL_VGA_DEVICE(0x4681, info), \
> + INTEL_VGA_DEVICE(0x4682, info), \
> + INTEL_VGA_DEVICE(0x4683, info), \
> + INTEL_VGA_DEVICE(0x4690, info), \
> + INTEL_VGA_DEVICE(0x4691, info), \
> + INTEL_VGA_DEVICE(0x4692, info), \
> + INTEL_VGA_DEVICE(0x4693, info), \
> + INTEL_VGA_DEVICE(0x4698, info), \
> + INTEL_VGA_DEVICE(0x4699, info)
> +
> #endif /* _I915_PCIIDS_H */
> --
> 2.27.0
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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