From: Matt Roper <matthew.d.ro...@intel.com>

ADL-S has instances of the PHY_MISC register on the first three PHYs,
but only expects the "DE to IO Comp Pwr Down" bit (the only bit we touch
on non-EHL platforms) to be programmed for PHY A.

Bspec: 50107
Cc: Lucas De Marchi <lucas.demar...@intel.com>
Cc: Jani Nikula <jani.nik...@intel.com>
Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
Cc: Imre Deak <imre.d...@intel.com>
Cc: Aditya Swarup <aditya.swa...@intel.com>
Signed-off-by: Matt Roper <matthew.d.ro...@intel.com>
Signed-off-by: Aditya Swarup <aditya.swa...@intel.com>
---
 drivers/gpu/drm/i915/display/intel_combo_phy.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c 
b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index 55d2d2d9efbb..5a71adbd7a4d 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -187,10 +187,16 @@ static bool has_phy_misc(struct drm_i915_private *i915, 
enum phy phy)
         * Some platforms only expect PHY_MISC to be programmed for PHY-A and
         * PHY-B and may not even have instances of the register for the
         * other combo PHY's.
+        *
+        * ADL-S technically has three instances of PHY_MISC, but only requires
+        * that we program it for PHY A.
         */
-       if (IS_JSL_EHL(i915) ||
-           IS_ROCKETLAKE(i915) ||
-           IS_DG1(i915))
+
+       if (IS_ALDERLAKE_S(i915))
+               return phy == PHY_A;
+       else if (IS_JSL_EHL(i915) ||
+                IS_ROCKETLAKE(i915) ||
+                IS_DG1(i915))
                return phy < PHY_C;
 
        return true;
-- 
2.27.0

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