From: Anusha Srivatsa <anusha.sriva...@intel.com>

ADLS follows ICP/TGP like interrupts. Reuse hpd_icp and introduce
ADLS DDI and HPD masks for setting up hpd interrupts.

Cc: Lucas De Marchi <lucas.demar...@intel.com>
Cc: Jani Nikula <jani.nik...@intel.com>
Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
Cc: Imre Deak <imre.d...@intel.com>
Cc: Matt Roper <matthew.d.ro...@intel.com>
Cc: José Roberto de Souza <jose.so...@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com>
Signed-off-by: Aditya Swarup <aditya.swa...@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 20 ++++++++++++++++----
 drivers/gpu/drm/i915/i915_reg.h |  3 +++
 2 files changed, 19 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b753c77c9a77..9033221995ad 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -179,8 +179,9 @@ static void intel_hpd_init_pins(struct drm_i915_private 
*dev_priv)
        if (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv))
                return;
 
-       if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv) ||
-           HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv))
+       if (HAS_PCH_ADP(dev_priv) || HAS_PCH_TGP(dev_priv) ||
+           HAS_PCH_JSP(dev_priv) || HAS_PCH_ICP(dev_priv) ||
+           HAS_PCH_MCC(dev_priv))
                hpd->pch_hpd = hpd_icp;
        else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_SPT(dev_priv))
                hpd->pch_hpd = hpd_spt;
@@ -1864,7 +1865,10 @@ static void icp_irq_handler(struct drm_i915_private 
*dev_priv, u32 pch_iir)
        u32 ddi_hotplug_trigger, tc_hotplug_trigger;
        u32 pin_mask = 0, long_mask = 0;
 
-       if (HAS_PCH_TGP(dev_priv)) {
+       if (IS_ALDERLAKE_S(dev_priv)) {
+               ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ADLS;
+               tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
+       } else if (HAS_PCH_TGP(dev_priv)) {
                ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
                tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;
        } else if (HAS_PCH_JSP(dev_priv)) {
@@ -3252,6 +3256,12 @@ static void jsp_hpd_irq_setup(struct drm_i915_private 
*dev_priv)
                          TGP_DDI_HPD_ENABLE_MASK, 0);
 }
 
+static void adls_hpd_irq_setup(struct drm_i915_private *dev_priv)
+{
+       icp_hpd_irq_setup(dev_priv,
+                         ADLS_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE_MASK);
+}
+
 static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
 {
        u32 hotplug;
@@ -4162,7 +4172,9 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
                if (I915_HAS_HOTPLUG(dev_priv))
                        dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
        } else {
-               if (HAS_PCH_JSP(dev_priv))
+               if (IS_ALDERLAKE_S(dev_priv))
+                       dev_priv->display.hpd_irq_setup = adls_hpd_irq_setup;
+               else if (HAS_PCH_JSP(dev_priv))
                        dev_priv->display.hpd_irq_setup = jsp_hpd_irq_setup;
                else if (HAS_PCH_MCC(dev_priv))
                        dev_priv->display.hpd_irq_setup = mcc_hpd_irq_setup;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 83ddea1cd174..f6b844ca7a9f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8343,6 +8343,7 @@ enum {
                                         SDE_TC_HOTPLUG_ICP(PORT_TC3) | \
                                         SDE_TC_HOTPLUG_ICP(PORT_TC2) | \
                                         SDE_TC_HOTPLUG_ICP(PORT_TC1))
+#define SDE_DDI_MASK_ADLS               SDE_DDI_HOTPLUG_ICP(PORT_A)
 
 #define SDEISR  _MMIO(0xc4000)
 #define SDEIMR  _MMIO(0xc4004)
@@ -8438,6 +8439,8 @@ enum {
                                         ICP_TC_HPD_ENABLE(PORT_TC5) | \
                                         ICP_TC_HPD_ENABLE_MASK)
 
+#define ADLS_DDI_HPD_ENABLE_MASK        SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A)
+
 #define _PCH_DPLL_A              0xc6014
 #define _PCH_DPLL_B              0xc6018
 #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
-- 
2.27.0

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