According to configdb the same register as for gen4 also exists on
pnv. Try to use it.
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vet...@ffwll.ch>
---
drivers/gpu/drm/i915/intel_uncore.c | 20 +++++++++++++++-----
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 8f5bc86..859c84d 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -566,11 +566,21 @@ int intel_gpu_reset(struct drm_device *dev)
{
switch (INTEL_INFO(dev)->gen) {
case 7:
- case 6: return gen6_do_reset(dev);
- case 5: return ironlake_do_reset(dev);
- case 4: return i965_do_reset(dev);
- case 2: return i8xx_do_reset(dev);
- default: return -ENODEV;
+ case 6:
+ return gen6_do_reset(dev);
+ case 5:
+ return ironlake_do_reset(dev);
+ case 4:
+ return i965_do_reset(dev);
+ case 3:
+ if (IS_PINEVIEW(dev))
+ return i965_do_reset(dev);
+ else
+ return -ENODEV;
+ case 2:
+ return i8xx_do_reset(dev);
+ default:
+ return -ENODEV;
}
}
--
1.8.3.2
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