On Tue, Aug 25, 2020 at 07:57:24PM -0700, clinton.a.tay...@intel.com wrote:
> From: Clint Taylor <clinton.a.tay...@intel.com>
>
> Enable HW Default flip for small PL.
>
> bspec: 52890
> bspec: 53508
> bspec: 53273
>
> v2: rebase to drm-tip
> v3: move from ctx to gt workarounds. Remove whitelist.
> v4: move to rcs WA init
>
> Cc: Matt Atwood <matthew.s.atw...@intel.com>
> Cc: Matt Roper <matthew.d.ro...@intel.com>
> Cc: José Roberto de Souza <jose.so...@intel.com>
> Signed-off-by: Clint Taylor <clinton.a.tay...@intel.com>
Reviewed-by: Matt Roper <matthew.d.ro...@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +++++++
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 2 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index a3f72b75c61e..b0a7cb056633 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1725,6 +1725,13 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
> struct i915_wa_list *wal)
> FF_DOP_CLOCK_GATE_DISABLE);
> }
>
> + if (IS_GEN(i915, 12)) {
> + /* Wa_1406941453:gen12 */
> + wa_masked_en(wal,
> + GEN10_SAMPLER_MODE,
> + ENABLE_SMALLPL);
> + }
> +
> if (IS_GEN(i915, 11)) {
> /* This is not an Wa. Enable for better image quality */
> wa_masked_en(wal,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index ac691927e29d..ab4b1abd4364 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9315,6 +9315,7 @@ enum {
> #define GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC (1 << 7)
>
> #define GEN10_SAMPLER_MODE _MMIO(0xE18C)
> +#define ENABLE_SMALLPL REG_BIT(15)
> #define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5)
>
> /* IVYBRIDGE DPF */
> --
> 2.28.0
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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