On Fri, 2020-06-26 at 15:11 +0100, Mun, Gwan-gyeong wrote:
> On Thu, 2020-06-25 at 18:01 -0700, José Roberto de Souza wrote:
> > This registers will be used to implement PSR2 manual
> > tracking/selective
> > fetch.
> >
> > v2:
> > - Fixed typo in _PLANE_SEL_FETCH_BASE
> > - Renamed PSR2_MAN_TRK_CTL bits to better match spec names
> > - Renamed _PLANE_SEL_FETCH_* to better match spec names
> >
> > BSpec: 55229
> > BSpec: 50424
> > BSpec: 50420
> > Cc: Gwan-gyeong Mun <gwan-gyeong....@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.so...@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 68 ++++++++++++++++++++++++++++++-
> > --
> > 1 file changed, 63 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index f09120cac89a..8b6eb42b63db 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -4585,6 +4585,18 @@ enum {
> > #define PSR2_SU_STATUS_MASK(frame) (0x3ff <<
> > PSR2_SU_STATUS_SHIFT(frame))
> > #define PSR2_SU_STATUS_FRAMES 8
> >
> > +#define _PSR2_MAN_TRK_CTL_A 0x60910
> > +#define _PSR2_MAN_TRK_CTL_EDP 0x6f910
> > +#define PSR2_MAN_TRK_CTL(tran) _MMIO_T
> > RANS2(tran, _PSR2_MAN_TRK_CTL_A)
> > +#define PSR2_MAN_TRK_CTL_ENABLE REG_BIT(31)
> > +#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(30,
> > 21)
> > +#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(
> > PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
> > +#define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GEN
> > MASK(20, 11)
> > +#define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIE
> > LD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)
> > +#define PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT
> > (3)
> > +#define PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(2)
> > +#define PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(1)
> > +
> > /* VGA port control */
> > #define ADPA _MMIO(0x61100)
> > #define PCH_ADPA _MMIO(0xe1100)
> > @@ -7148,7 +7160,52 @@ enum {
> > #define PLANE_COLOR_CTL(pipe, plane) \
> > _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe),
> > _PLANE_COLOR_CTL_2(pipe))
> >
> > -#/* SKL new cursor registers */
> > +#define _SEL_FETCH_PLANE_BASE_1_A 0x70890
> > +#define _SEL_FETCH_PLANE_BASE_2_A 0x708B0
> > +#define _SEL_FETCH_PLANE_BASE_3_A 0x708D0
> > +#define _SEL_FETCH_PLANE_BASE_4_A 0x708F0
> > +#define _SEL_FETCH_PLANE_BASE_5_A 0x70920
> > +#define _SEL_FETCH_PLANE_BASE_6_A 0x70940
> > +#define _SEL_FETCH_PLANE_BASE_7_A 0x70960
> > +#define _SEL_FETCH_PLANE_BASE_CUR_A 0x70880
> > +#define _SEL_FETCH_PLANE_BASE_1_B 0x70990
> > +
> > +#define _SEL_FETCH_PLANE_BASE_A(plane) _PICK(plane, \
> > + _SEL_FETCH_PLANE_BASE_1_A,
> > \
> > + _SEL_FETCH_PLANE_BASE_2_A,
> > \
> > + _SEL_FETCH_PLANE_BASE_3_A,
> > \
> > + _SEL_FETCH_PLANE_BASE_4_A,
> > \
> > + _SEL_FETCH_PLANE_BASE_5_A,
> > \
> > + _SEL_FETCH_PLANE_BASE_6_A,
> > \
> > + _SEL_FETCH_PLANE_BASE_7_A,
> > \
> > + _SEL_FETCH_PLANE_BASE_CUR_
> > A)
> > +#define _SEL_FETCH_PLANE_BASE_1(pipe) _PIPE(pipe,
> > _SEL_FETCH_PLANE_BASE_1_A, _SEL_FETCH_PLANE_BASE_1_B)
> > +#define _SEL_FETCH_PLANE_BASE(pipe, plane)
> > (_SEL_FETCH_PLANE_BASE_1(pipe) - \
> > + _SEL_FETCH_PLANE_BASE_1_A +
> > \
> > + _SEL_FETCH_PLANE_BASE_A(pla
> > ne))
> > +
> > +#define _SEL_FETCH_PLANE_CTL_1_A 0x70890
> > +#define PLANE_SEL_FETCH_CTL(pipe, plane)
> > _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
> > + _SEL_FETCH_PLANE_CTL_1_A
> > - \
> > + _SEL_FETCH_PLANE_BASE_1_
> > A)
> > +#define PLANE_SET_FETCH_CTL_ENABLE REG_BIT(31)
> it seems a typo of "PLANE_SEL_FETCH_CTL_ENABLE",
> except for this line, looks good to me.
Yep, thanks for catch up this.
>
> Reviewed-by: Gwan-gyeong Mun <gwan-gyeong....@intel.com>
> > +
> > +#define _SEL_FETCH_PLANE_POS_1_A 0x70894
> > +#define PLANE_SEL_FETCH_POS(pipe, plane)
> > _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
> > + _SEL_FETCH_PLANE_POS_1_A
> > - \
> > + _SEL_FETCH_PLANE_BASE_1_
> > A)
> > +
> > +#define _SEL_FETCH_PLANE_SIZE_1_A 0x70898
> > +#define PLANE_SEL_FETCH_SIZE(pipe, plane)
> > _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
> > + _SEL_FETCH_PLANE_SIZE_1
> > _A - \
> > + _SEL_FETCH_PLANE_BASE_1
> > _A)
> > +
> > +#define _SEL_FETCH_PLANE_OFFSET_1_A 0x7089C
> > +#define PLANE_SEL_FETCH_OFFSET(pipe, plane)
> > _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
> > + _SEL_FETCH_PLANE_OFFS
> > ET_1_A - \
> > + _SEL_FETCH_PLANE_BASE
> > _1_A)
> > +
> > +/* SKL new cursor registers */
> > #define _CUR_BUF_CFG_A 0x7017c
> > #define _CUR_BUF_CFG_B 0x7117c
> > #define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A,
> > _CUR_BUF_CFG_B)
> > @@ -7794,11 +7851,12 @@ enum {
> > # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5)
> > # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2)
> >
> > -#define CHICKEN_PAR1_1 _MMIO(0x42080)
> > +#define CHICKEN_PAR1_1 _MMIO(0x42080)
> > #define SKL_DE_COMPRESSED_HASH_MODE (1 << 15)
> > -#define DPA_MASK_VBLANK_SRD (1 << 15)
> > -#define FORCE_ARB_IDLE_PLANES (1 << 14)
> > -#define SKL_EDP_PSR_FIX_RDWRAP (1 << 3)
> > +#define DPA_MASK_VBLANK_SRD (1 << 15)
> > +#define FORCE_ARB_IDLE_PLANES (1 << 14)
> > +#define SKL_EDP_PSR_FIX_RDWRAP (1 << 3)
> > +#define IGNORE_PSR2_HW_TRACKING (1 << 1)
> >
> > #define CHICKEN_PAR2_1 _MMIO(0x42090)
> > #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14)
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