On Sat, Jul 06, 2013 at 12:52:06PM +0200, Daniel Vetter wrote: > Section 1.5.4, "DPLL A Control Register" from Bspec about bit 23 > "FPA0/A1 P2 Clock Divide": > > 0 = Divide by 2 > 1 = Divide by 4. This bit must be set in DVO non-gang mode > > So copy the current limits (which should be good for i8xx) and create > a new set for dvo encoders. > > Signed-off-by: Daniel Vetter <daniel.vet...@ffwll.ch> Reviewed-by: Chris Wilson <ch...@chris-wilson.oc.uk> -Chris
-- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
