> -----Original Message----- > From: Jani Nikula <jani.nik...@intel.com> > Sent: Friday, March 27, 2020 6:12 PM > To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org > Cc: Nikula, Jani <jani.nik...@intel.com>; Alex Deucher > <alexdeuc...@gmail.com>; Harry Wentland <hwent...@amd.com>; Navare, > Manasi D <manasi.d.nav...@intel.com>; Kulkarni, Vandita > <vandita.kulka...@intel.com> > Subject: [PATCH RESEND 1/7] drm/dsc: use rc_model_size from DSC config for > PPS > > The PPS is supposed to reflect the DSC config instead of hard coding the > rc_model_size. Make it so. > > Currently all users of drm_dsc_pps_payload_pack() hard code the size to > 8192 also in the DSC config, so this change should have no impact, other than > allowing the drivers to use other sizes as needed. > > Cc: Alex Deucher <alexdeuc...@gmail.com> > Cc: Harry Wentland <hwent...@amd.com> > Cc: Manasi Navare <manasi.d.nav...@intel.com> > Cc: Vandita Kulkarni <vandita.kulka...@intel.com> > Signed-off-by: Jani Nikula <jani.nik...@intel.com>
Looks good to me. Reviewed-by: Vandita Kulkarni <vandita.kulka...@intel.com> > --- > drivers/gpu/drm/drm_dsc.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/drm_dsc.c b/drivers/gpu/drm/drm_dsc.c index > 4a475d9696ff..09afbc01ea94 100644 > --- a/drivers/gpu/drm/drm_dsc.c > +++ b/drivers/gpu/drm/drm_dsc.c > @@ -186,8 +186,7 @@ void drm_dsc_pps_payload_pack(struct > drm_dsc_picture_parameter_set *pps_payload, > pps_payload->flatness_max_qp = dsc_cfg->flatness_max_qp; > > /* PPS 38, 39 */ > - pps_payload->rc_model_size = > - cpu_to_be16(DSC_RC_MODEL_SIZE_CONST); > + pps_payload->rc_model_size = cpu_to_be16(dsc_cfg->rc_model_size); > > /* PPS 40 */ > pps_payload->rc_edge_factor = DSC_RC_EDGE_FACTOR_CONST; > -- > 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
