From: Ville Syrjälä <ville.syrj...@linux.intel.com>
Pull the common parts of intel_dp_compute_link_config_wide()
and intel_dp_compute_link_config_fast() into a shared helper
to avoid duplicated code.
Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 76 ++++++++++++++-----------
1 file changed, 44 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 85abcce492ca..8491ce8b8c15 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2014,34 +2014,47 @@ static int intel_dp_output_bpp(const struct
intel_crtc_state *crtc_state, int bp
return bpp;
}
+static bool
+intel_dp_link_config_valid(const struct intel_crtc_state *crtc_state,
+ int bpp, int link_clock, int lane_count)
+{
+ const struct drm_display_mode *adjusted_mode =
+ &crtc_state->hw.adjusted_mode;
+ int output_bpp = intel_dp_output_bpp(crtc_state, bpp);
+ int mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
+ output_bpp);
+ int link_avail = intel_dp_max_data_rate(link_clock, lane_count);
+
+ return mode_rate <= link_avail;
+}
+
/* Optimize link config in order: max bpp, min clock, min lanes */
static int
intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
- struct intel_crtc_state *pipe_config,
+ struct intel_crtc_state *crtc_state,
const struct link_config_limits *limits)
{
- struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
- int bpp, clock, lane_count;
- int mode_rate, link_clock, link_avail;
+ int bpp;
for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
- int output_bpp = intel_dp_output_bpp(pipe_config, bpp);
+ int clock;
- mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
- output_bpp);
+ for (clock = limits->min_clock;
+ clock <= limits->max_clock;
+ clock++) {
+ int lane_count;
- for (clock = limits->min_clock; clock <= limits->max_clock;
clock++) {
for (lane_count = limits->min_lane_count;
lane_count <= limits->max_lane_count;
lane_count <<= 1) {
- link_clock = intel_dp->common_rates[clock];
- link_avail = intel_dp_max_data_rate(link_clock,
- lane_count);
+ int link_clock = intel_dp->common_rates[clock];
- if (mode_rate <= link_avail) {
- pipe_config->lane_count = lane_count;
- pipe_config->pipe_bpp = bpp;
- pipe_config->port_clock = link_clock;
+ if (intel_dp_link_config_valid(crtc_state, bpp,
+ link_clock,
+ lane_count)) {
+ crtc_state->pipe_bpp = bpp;
+ crtc_state->port_clock = link_clock;
+ crtc_state->lane_count = lane_count;
return 0;
}
@@ -2055,31 +2068,30 @@ intel_dp_compute_link_config_wide(struct intel_dp
*intel_dp,
/* Optimize link config in order: max bpp, min lanes, min clock */
static int
intel_dp_compute_link_config_fast(struct intel_dp *intel_dp,
- struct intel_crtc_state *pipe_config,
+ struct intel_crtc_state *crtc_state,
const struct link_config_limits *limits)
{
- const struct drm_display_mode *adjusted_mode =
&pipe_config->hw.adjusted_mode;
- int bpp, clock, lane_count;
- int mode_rate, link_clock, link_avail;
+ int bpp;
for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
- int output_bpp = intel_dp_output_bpp(pipe_config, bpp);
-
- mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
- output_bpp);
+ int lane_count;
for (lane_count = limits->min_lane_count;
lane_count <= limits->max_lane_count;
lane_count <<= 1) {
- for (clock = limits->min_clock; clock <=
limits->max_clock; clock++) {
- link_clock = intel_dp->common_rates[clock];
- link_avail = intel_dp_max_data_rate(link_clock,
- lane_count);
-
- if (mode_rate <= link_avail) {
- pipe_config->lane_count = lane_count;
- pipe_config->pipe_bpp = bpp;
- pipe_config->port_clock = link_clock;
+ int clock;
+
+ for (clock = limits->min_clock;
+ clock <= limits->max_clock;
+ clock++) {
+ int link_clock = intel_dp->common_rates[clock];
+
+ if (intel_dp_link_config_valid(crtc_state, bpp,
+ link_clock,
+ lane_count)) {
+ crtc_state->pipe_bpp = bpp;
+ crtc_state->port_clock = link_clock;
+ crtc_state->lane_count = lane_count;
return 0;
}
--
2.24.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
