Matt Roper <matthew.d.ro...@intel.com> writes:
> The bspec documents multiple MCR ranges; make sure they're all captured
> by the driver.
>
> Bspec: 13991, 52079
> Fixes: 592a7c5e082e ("drm/i915: Extend non readable mcr range")
Yeah it seems that the ranges drip feed into documentation slowly.
> Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com>
> Signed-off-by: Matt Roper <matthew.d.ro...@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuopp...@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 25 ++++++++++++++++++---
> 1 file changed, 22 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 391f39b1fb26..3e352e2a5b79 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1648,15 +1648,34 @@ create_scratch(struct i915_address_space *vm, int
> count)
> return ERR_PTR(err);
> }
>
> +static const struct {
> + u32 start;
> + u32 end;
> +} mcr_ranges_gen8[] = {
> + { .start = 0x5500, .end = 0x55ff },
> + { .start = 0x7000, .end = 0x7fff },
> + { .start = 0x9400, .end = 0x97ff },
> + { .start = 0xb000, .end = 0xb3ff },
> + { .start = 0xe000, .end = 0xe7ff },
> + {},
> +};
> +
> static bool mcr_range(struct drm_i915_private *i915, u32 offset)
> {
> + int i;
> +
> + if (INTEL_GEN(i915) < 8)
> + return false;
> +
> /*
> - * Registers in this range are affected by the MCR selector
> + * Registers in these ranges are affected by the MCR selector
> * which only controls CPU initiated MMIO. Routing does not
> * work for CS access so we cannot verify them on this path.
> */
> - if (INTEL_GEN(i915) >= 8 && (offset >= 0xb000 && offset <= 0xb4ff))
> - return true;
> + for (i = 0; mcr_ranges_gen8[i].start; i++)
> + if (offset >= mcr_ranges_gen8[i].start &&
> + offset <= mcr_ranges_gen8[i].end)
> + return true;
>
> return false;
> }
> --
> 2.24.1
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