On Wed, Feb 05, 2020 at 06:08:50PM -0800, José Roberto de Souza wrote:
> From: Radhakrishna Sripada <radhakrishna.srip...@intel.com>
>
> Platforms without fences don't have FBC host tracking and those
> registers are marked as reserved in those platforms.
>
> v2: checking num_fences to write to FBC fence registers (Ville)
>
> Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
> Cc: Matt Roper <matthew.d.ro...@intel.com>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com>
> Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.srip...@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demar...@intel.com>
> Signed-off-by: José Roberto de Souza <jose.so...@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_fbc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 3a9e41e93ebf..fa8fca1a6b7c 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -320,7 +320,7 @@ static void gen7_fbc_activate(struct drm_i915_private
> *dev_priv)
> SNB_CPU_FENCE_ENABLE | params->fence_id);
> intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET,
> params->crtc.fence_y_offset);
> - } else {
> + } else if (dev_priv->ggtt.num_fences) {
> intel_de_write(dev_priv, SNB_DPFC_CTL_SA, 0);
> intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET, 0);
> }
> --
> 2.25.0
--
Ville Syrjälä
Intel
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