From: Ville Syrjälä <ville.syrj...@linux.intel.com>
Move the DSB tail cacheline alignment to a helper. No need to pollute
the caller with mundane details like this.
Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dsb.c | 20 ++++++++++++++------
1 file changed, 14 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index 45acfd91ee74..56790fae6386 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -254,6 +254,18 @@ void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t
reg, u32 val)
i915_mmio_reg_offset(reg);
}
+static u32 intel_dsb_align_tail(struct intel_dsb *dsb)
+{
+ u32 tail;
+
+ tail = ALIGN(dsb->free_pos * 4, CACHELINE_BYTES);
+ if (tail > dsb->free_pos * 4)
+ memset(&dsb->cmd_buf[dsb->free_pos], 0,
+ (tail - dsb->free_pos * 4));
+
+ return tail;
+}
+
/**
* intel_dsb_commit() - Trigger workload execution of DSB.
* @dsb: intel_dsb structure.
@@ -269,14 +281,10 @@ void intel_dsb_commit(struct intel_dsb *dsb)
enum pipe pipe = crtc->pipe;
u32 tail;
- if (!dsb->free_pos)
+ tail = intel_dsb_align_tail(dsb);
+ if (tail == 0)
return;
- tail = ALIGN(dsb->free_pos * 4, CACHELINE_BYTES);
- if (tail > dsb->free_pos * 4)
- memset(&dsb->cmd_buf[dsb->free_pos], 0,
- (tail - dsb->free_pos * 4));
-
if (is_dsb_busy(dsb)) {
DRM_ERROR("DSB engine is busy.\n");
goto reset;
--
2.24.1
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