From VBT 228+ this is block that PSR and other power saving
features configuration should be read from.

v3:
Using DRRS from this new block

v4:
Using BIT()
Fixing DRRS comment in parse_power_conservation_features()

Cc: Matt Roper <matthew.d.ro...@intel.com>
Cc: Gwan-gyeong Mun <gwan-gyeong....@intel.com>
Reviewed-by: Matt Roper <matthew.d.ro...@intel.com>
Signed-off-by: José Roberto de Souza <jose.so...@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bios.c     | 38 +++++++++++++++++--
 drivers/gpu/drm/i915/display/intel_vbt_defs.h | 29 ++++++++++++++
 2 files changed, 63 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c 
b/drivers/gpu/drm/i915/display/intel_bios.c
index f6a9a5ccb556..70e644082bec 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -659,16 +659,45 @@ parse_driver_features(struct drm_i915_private *dev_priv,
                        dev_priv->vbt.int_lvds_support = 0;
        }
 
-       DRM_DEBUG_KMS("DRRS State Enabled:%d\n", driver->drrs_enabled);
+       if (bdb->version < 228) {
+               DRM_DEBUG_KMS("DRRS State Enabled:%d\n", driver->drrs_enabled);
+               /*
+                * If DRRS is not supported, drrs_type has to be set to 0.
+                * This is because, VBT is configured in such a way that
+                * static DRRS is 0 and DRRS not supported is represented by
+                * driver->drrs_enabled=false
+                */
+               if (!driver->drrs_enabled)
+                       dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED;
+
+               dev_priv->vbt.psr.enable = driver->psr_enabled;
+       }
+}
+
+static void
+parse_power_conservation_features(struct drm_i915_private *dev_priv,
+                                 const struct bdb_header *bdb)
+{
+       const struct bdb_lfp_power *power;
+       u8 panel_type = dev_priv->vbt.panel_type;
+
+       if (bdb->version < 228)
+               return;
+
+       power = find_section(bdb, BDB_LVDS_POWER);
+       if (!power)
+               return;
+
+       dev_priv->vbt.psr.enable = power->psr & BIT(panel_type);
+
        /*
         * If DRRS is not supported, drrs_type has to be set to 0.
         * This is because, VBT is configured in such a way that
         * static DRRS is 0 and DRRS not supported is represented by
-        * driver->drrs_enabled=false
+        * power->drrs & BIT(panel_type)=false
         */
-       if (!driver->drrs_enabled)
+       if (!(power->drrs & BIT(panel_type)))
                dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED;
-       dev_priv->vbt.psr.enable = driver->psr_enabled;
 }
 
 static void
@@ -1973,6 +2002,7 @@ void intel_bios_init(struct drm_i915_private *dev_priv)
        parse_lfp_backlight(dev_priv, bdb);
        parse_sdvo_panel_data(dev_priv, bdb);
        parse_driver_features(dev_priv, bdb);
+       parse_power_conservation_features(dev_priv, bdb);
        parse_edp(dev_priv, bdb);
        parse_psr(dev_priv, bdb);
        parse_mipi_config(dev_priv, bdb);
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h 
b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index f0338da3a82a..98b71dc32d2a 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -793,6 +793,35 @@ struct bdb_lfp_backlight_data {
        struct lfp_backlight_control_method backlight_control[16];
 } __packed;
 
+/*
+ * Block 44 - LFP Power Conservation Features Block
+ */
+
+struct als_data_entry {
+       u16 backlight_adjust;
+       u16 lux;
+} __packed;
+
+struct agressiveness_profile_entry {
+       u8 dpst_agressiveness : 4;
+       u8 lace_agressiveness : 4;
+} __packed;
+
+struct bdb_lfp_power {
+       u8 lfp_feature_bits;
+       struct als_data_entry als[5];
+       u8 lace_aggressiveness_profile;
+       u16 dpst;
+       u16 psr;
+       u16 drrs;
+       u16 lace_support;
+       u16 adt;
+       u16 dmrrs;
+       u16 adb;
+       u16 lace_enabled_status;
+       struct agressiveness_profile_entry aggressivenes[16];
+} __packed;
+
 /*
  * Block 52 - MIPI Configuration Block
  */
-- 
2.24.0

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