> -----Original Message-----
> From: Chris Wilson <ch...@chris-wilson.co.uk>
> Sent: Thursday, November 21, 2019 3:45 PM
> To: Tang, CQ <cq.t...@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: igt-...@lists.freedesktop.org
> Subject: RE: [Intel-gfx] [PATCH i-g-t 5/9] i915/gem_ctx_isolation: Check
> engine relative registers
>
> Quoting Tang, CQ (2019-11-21 21:07:13)
> >
> >
> > > -----Original Message-----
> > > From: Intel-gfx <intel-gfx-boun...@lists.freedesktop.org> On Behalf
> > > Of Chris Wilson
> > > Sent: Wednesday, November 13, 2019 4:53 AM
> > > To: intel-gfx@lists.freedesktop.org
> > > Cc: igt-...@lists.freedesktop.org
> > > Subject: [Intel-gfx] [PATCH i-g-t 5/9] i915/gem_ctx_isolation: Check
> > > engine @@ -248,6 +238,7 @@ static void tmpl_regs(int fd, {
> > > const unsigned int gen_bit = 1 <<
> > > intel_gen(intel_get_drm_devid(fd));
> > > const unsigned int engine_bit = ENGINE(e->class, e->instance);
> > > + const uint32_t mmio_base = gem_engine_mmio_base(fd, e->name);
> >
> > Chris, I tried to test this patch, but "gem_engine_mmio_base()" above is
> not defined.
> > Can you check?
>
> Did you perchance look at patch 4?
Thanks, find this one:
[i-g-t,4/9] i915: Start putting the mmio_base to wider use
--CQ
> -Chris
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