In the event a platform does not properly implement reset,
do not go through reset flows for engine domains to avoid
an unlikely situation where writes are accepted but register
values are never cleared, as this can result in GPU wedges
in these cases.
Signed-off-by: Stuart Summers <stuart.summ...@intel.com>
---
drivers/gpu/drm/i915/gt/intel_reset.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
b/drivers/gpu/drm/i915/gt/intel_reset.c
index 0388f9375366..0454e01e063c 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -270,6 +270,12 @@ static int gen6_hw_domain_reset(struct intel_gt *gt, u32
hw_domain_mask)
struct intel_uncore *uncore = gt->uncore;
int err;
+ if (!i915_modparams.reset) {
+ DRM_DEBUG_DRIVER("Skipping 0x%08x engines reset\n",
+ hw_domain_mask);
+ return 0;
+ }
+
/*
* GEN6_GDRST is not in the gt power well, no need to check
* for fifo space for the write or forcewake the chip for
@@ -494,6 +500,13 @@ static int gen8_engine_reset_prepare(struct
intel_engine_cs *engine)
return 0;
}
+ if (!i915_modparams.reset) {
+ DRM_DEBUG_DRIVER("Skipping %s reset request {request: %08x,
RESET_CTL: %08x}\n",
+ engine->name, request,
+ intel_uncore_read_fw(uncore, reg));
+ return 0;
+ }
+
intel_uncore_write_fw(uncore, reg, _MASKED_BIT_ENABLE(request));
ret = __intel_wait_for_register_fw(uncore, reg, mask, ack,
700, 0, NULL);
--
2.22.0
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