At TGL A0 stepping, FF_MODE2 register read back is broken, hence
disabling the WA verification.
Helper function called wa_write_masked_or_no_verify is defined for the
same purpose.
Signed-off-by: Ramalingam C <ramalinga...@intel.com>
cc: Tvrtko Ursulin <tvrtko.ursu...@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 20 +++++++++++++++++++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 93efefa205d6..1698330c6f23 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -160,6 +160,20 @@ wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t
reg, u32 mask,
_wa_add(wal, &wa);
}
+static void
+wa_write_masked_or_no_verify(struct i915_wa_list *wal, i915_reg_t reg, u32
mask,
+ u32 val)
+{
+ struct i915_wa wa = {
+ .reg = reg,
+ .mask = mask,
+ .val = val,
+ .read = 0,
+ };
+
+ _wa_add(wal, &wa);
+}
+
static void
wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
{
@@ -578,7 +592,11 @@ static void tgl_ctx_workarounds_init(struct
intel_engine_cs *engine,
val = intel_uncore_read(engine->uncore, FF_MODE2);
val &= ~FF_MODE2_TDS_TIMER_MASK;
val |= FF_MODE2_TDS_TIMER_128;
- wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val);
+ if (IS_TGL_REVID(engine->uncore->i915, 0, TGL_REVID_A0))
+ wa_write_masked_or_no_verify(wal, FF_MODE2,
+ FF_MODE2_TDS_TIMER_MASK, val);
+ else
+ wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val);
}
static void
--
2.20.1
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