In case of dual link, we get the TE on slave.
So clear the TE on slave DSI IIR.

Signed-off-by: Vandita Kulkarni <vandita.kulka...@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 62 +++++++++++++++++++++++++++++++++
 1 file changed, 62 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index f27afde409bf..34a06876a2d7 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2230,6 +2230,62 @@ gen8_de_misc_irq_handler(struct drm_i915_private 
*dev_priv, u32 iir)
                DRM_ERROR("Unexpected DE Misc interrupt\n");
 }
 
+void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv,
+                                   u32 iir_value)
+{
+       enum pipe pipe = INVALID_PIPE;
+       enum transcoder dsi_trans;
+       enum port port;
+       u32 val, tmp;
+
+       /*
+        * Incase of dual link, TE comes from DSI_1
+        * this is to check if dual link is enabled
+        */
+       val = I915_READ(TRANS_DDI_FUNC_CTL2(TRANSCODER_DSI_0));
+       val &= PORT_SYNC_MODE_ENABLE;
+
+       /*
+        * if dual link is enabled, then read DSI_0
+        * transcoder registers
+        */
+       port = ((iir_value & DSI1_TE && val) || (iir_value & DSI0_TE)) ?
+                                                               PORT_A : PORT_B;
+       dsi_trans = (port == PORT_A) ? TRANSCODER_DSI_0 : TRANSCODER_DSI_1;
+
+       /* Check if DSI configured in command mode */
+       val = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans));
+       val = (val & OP_MODE_MASK) >> 28;
+
+       if (val) {
+               DRM_ERROR("DSI trancoder not configured in command mode\n");
+               return;
+       }
+
+       /* Get PIPE for handling VBLANK event */
+       val = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans));
+       switch (val & TRANS_DDI_EDP_INPUT_MASK) {
+       case TRANS_DDI_EDP_INPUT_A_ON:
+               pipe = PIPE_A;
+               break;
+       case TRANS_DDI_EDP_INPUT_B_ONOFF:
+               pipe = PIPE_B;
+               break;
+       case TRANS_DDI_EDP_INPUT_C_ONOFF:
+               pipe = PIPE_C;
+               break;
+       default:
+               DRM_ERROR("Invalid PIPE\n");
+       }
+
+       /* clear TE in dsi IIR */
+       port = (iir_value & DSI1_TE) ? PORT_B : PORT_A;
+       tmp = I915_READ(DSI_INTR_IDENT_REG(port));
+       I915_WRITE(DSI_INTR_IDENT_REG(port), tmp);
+
+       drm_handle_vblank(&dev_priv->drm, pipe);
+}
+
 static irqreturn_t
 gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 {
@@ -2294,6 +2350,12 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, 
u32 master_ctl)
                                found = true;
                        }
 
+                       if ((INTEL_GEN(dev_priv) >= 11) &&
+                               (iir & (DSI0_TE | DSI1_TE))) {
+                               gen11_dsi_te_interrupt_handler(dev_priv, iir);
+                               found = true;
+                       }
+
                        if (!found)
                                DRM_ERROR("Unexpected DE Port interrupt\n");
                }
-- 
2.21.0.5.gaeb582a

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