From: Paulo Zanoni <paulo.r.zan...@intel.com>
If we're using DP/eDP, adjusted_mode->clock may be just the port link
clock, but we also can't use mode->clock because it's wrong when we're
using the using panel fitter.
Signed-off-by: Paulo Zanoni <paulo.r.zan...@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8468b40..3ca020c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2021,6 +2021,7 @@ haswell_update_linetime_wm(struct drm_device *dev, struct
drm_crtc *crtc)
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
enum pipe pipe = intel_crtc->pipe;
struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
+ int target_clock;
u32 temp;
if (!intel_crtc_active(crtc)) {
@@ -2028,6 +2029,11 @@ haswell_update_linetime_wm(struct drm_device *dev,
struct drm_crtc *crtc)
return;
}
+ if (intel_crtc->config.pixel_target_clock)
+ target_clock = intel_crtc->config.pixel_target_clock;
+ else
+ target_clock = intel_crtc->config.adjusted_mode.clock;
+
temp = I915_READ(PIPE_WM_LINETIME(pipe));
temp &= ~PIPE_WM_LINETIME_MASK;
@@ -2035,7 +2041,7 @@ haswell_update_linetime_wm(struct drm_device *dev, struct
drm_crtc *crtc)
* row at the given clock rate, multiplied by 8.
* */
temp |= PIPE_WM_LINETIME_TIME(
- DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, mode->clock));
+ DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, target_clock));
/* IPS watermarks are only used by pipe A, and are ignored by
* pipes B and C. They are calculated similarly to the common
--
1.7.10.4
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