From: Michel Thierry <michel.thie...@intel.com> Enable Small PL for power benefit.
Signed-off-by: Michel Thierry <michel.thie...@intel.com> Signed-off-by: Lucas De Marchi <lucas.demar...@intel.com> Reviewed-by: Stuart Summers <stuart.summ...@intel.com> Reviewed-by: Radhakrishna Sripada <radhakrishna.srip...@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190713010940.17711-18-lucas.demar...@intel.com Link: https://patchwork.freedesktop.org/patch/msgid/20190726000226.26914-4-lucas.demar...@intel.com --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +++++++ drivers/gpu/drm/i915/i915_reg.h | 3 +++ 2 files changed, 10 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 41d0f786e06d..b77aaa563efc 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1257,6 +1257,13 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) { struct drm_i915_private *i915 = engine->i915; + if (IS_GEN(i915, 12)) { + /* Wa_1406941453:tgl */ + wa_masked_en(wal, + SAMPLER_MODE, + SAMPLER_ENABLE_SMALL_PL); + } + if (IS_GEN(i915, 11)) { /* This is not an Wa. Enable for better image quality */ wa_masked_en(wal, diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index bf37ecebc82f..af95f835f4f7 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8964,6 +8964,9 @@ enum { #define GEN9_DG_MIRROR_FIX_ENABLE (1 << 5) #define GEN9_CCS_TLB_PREFETCH_ENABLE (1 << 3) +#define SAMPLER_MODE _MMIO(0xe18c) +#define SAMPLER_ENABLE_SMALL_PL (1 << 15) + #define GEN8_ROW_CHICKEN _MMIO(0xe4f0) #define FLOW_CONTROL_ENABLE (1 << 15) #define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1 << 8) -- 2.23.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
