On Mon, Sep 16, 2019 at 10:11:45AM +0300, Gwan-gyeong Mun wrote:
> When BT.2020 Colorimetry output is used for DP, we should program BT.2020
> Colorimetry to MSA and VSC SDP. It adds output_colorspace to
> intel_crtc_state struct as a place holder of pipe's output colorspace.
> In order to distinguish needed colorimetry for VSC SDP, it adds
> intel_dp_needs_vsc_sdp function.
> If the output colorspace requires vsc sdp or output format is YCbCr 4:2:0,
> it uses MSA with VSC SDP.
>
> As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication of
> Color Encoding Format and Content Color Gamut] while sending
> BT.2020 Colorimetry signals we should program MSA MISC1 fields which
> indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
>
> v2: Remove useless parentheses
> v3: Addressed review comments from Ville
> - In order to checking output format and output colorspace on
> intel_dp_needs_vsc_sdp(), it passes entire intel_crtc_state struct
> value.
> - Remove a pointless variable.
>
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong....@intel.com>
> Reviewed-by: Uma Shankar <uma.shan...@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 7 +++--
> .../drm/i915/display/intel_display_types.h | 3 ++
> drivers/gpu/drm/i915/display/intel_dp.c | 29 ++++++++++++++++++-
> drivers/gpu/drm/i915/display/intel_dp.h | 1 +
> 4 files changed, 36 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 98d69febd8e3..8dc030650801 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1737,11 +1737,12 @@ void intel_ddi_set_pipe_settings(const struct
> intel_crtc_state *crtc_state)
> /*
> * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
> * of Color Encoding Format and Content Color Gamut] while sending
> - * YCBCR 420 signals we should program MSA MISC1 fields which
> - * indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
> + * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields
> + * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
> */
> - if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
> + if (intel_dp_needs_vsc_sdp(crtc_state))
> temp |= TRANS_MSA_USE_VSC_SDP;
> +
> I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index d5cc4b810d9e..4108570907d4 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -971,6 +971,9 @@ struct intel_crtc_state {
> /* Output format RGB/YCBCR etc */
> enum intel_output_format output_format;
>
> + /* Output colorspace sRGB/BT.2020 etc */
> + u32 output_colorspace;
Why are we duplicating this? It's already in the connector state no?
> +
> /* Output down scaling is done in LSPCON device */
> bool lspcon_downsampling;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index a2a0214f771a..3a8aef1c6036 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2187,6 +2187,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
> pipe_config->has_pch_encoder = true;
>
> pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
> + pipe_config->output_colorspace = intel_conn_state->base.colorspace;
> +
> if (lspcon->active)
> lspcon_ycbcr420_config(&intel_connector->base, pipe_config);
> else
> @@ -4448,6 +4450,31 @@ u8 intel_dp_dsc_get_slice_count(struct intel_dp
> *intel_dp,
> return 0;
> }
>
> +bool
> +intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state)
> +{
> + /*
> + * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
> + * of Color Encoding Format and Content Color Gamut], in order to
> + * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.
> + */
> + if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
> + return true;
> +
> + switch (crtc_state->output_colorspace) {
> + case DRM_MODE_COLORIMETRY_SYCC_601:
> + case DRM_MODE_COLORIMETRY_OPYCC_601:
> + case DRM_MODE_COLORIMETRY_BT2020_YCC:
> + case DRM_MODE_COLORIMETRY_BT2020_RGB:
> + case DRM_MODE_COLORIMETRY_BT2020_CYCC:
> + return true;
> + default:
> + break;
> + }
> +
> + return false;
> +}
> +
> static void
> intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp,
> const struct intel_crtc_state *crtc_state,
> @@ -4576,7 +4603,7 @@ void intel_dp_vsc_enable(struct intel_dp *intel_dp,
> const struct intel_crtc_state *crtc_state,
> const struct drm_connector_state *conn_state)
> {
> - if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_YCBCR420)
> + if (!intel_dp_needs_vsc_sdp(crtc_state))
> return;
>
> intel_dp_setup_vsc_sdp(intel_dp, crtc_state, conn_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
> b/drivers/gpu/drm/i915/display/intel_dp.h
> index be13cb395ef8..87883d0d5977 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -112,6 +112,7 @@ bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
> bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp);
> int intel_dp_link_required(int pixel_clock, int bpp);
> int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
> +bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state);
> void intel_dp_vsc_enable(struct intel_dp *intel_dp,
> const struct intel_crtc_state *crtc_state,
> const struct drm_connector_state *conn_state);
> --
> 2.23.0
--
Ville Syrjälä
Intel
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