Hi Chris, Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next] [cannot apply to v5.3-rc3 next-20190807] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Chris-Wilson/drm-i915-Flush-any-deferred-RCU-cleanup-before-switching-off-GEM/20190802-232023 base: git://anongit.freedesktop.org/drm-intel for-linux-next config: i386-defconfig (attached as .config) compiler: gcc-7 (Debian 7.4.0-10) 7.4.0 reproduce: # save the attached .config to linux build tree make ARCH=i386 If you fix the issue, kindly add following tag Reported-by: kbuild test robot <l...@intel.com> All errors (new ones prefixed by >>): drivers/gpu/drm/i915/i915_gem.c: In function 'i915_gem_init': >> drivers/gpu/drm/i915/i915_gem.c:1606:28: error: 'struct drm_i915_private' >> has no member named 'rq'; did you mean 'wq'? flush_workqueue(dev_priv->rq); ^~ wq vim +1606 drivers/gpu/drm/i915/i915_gem.c 1425 1426 int i915_gem_init(struct drm_i915_private *dev_priv) 1427 { 1428 int ret; 1429 1430 /* We need to fallback to 4K pages if host doesn't support huge gtt. */ 1431 if (intel_vgpu_active(dev_priv) && !intel_vgpu_has_huge_gtt(dev_priv)) 1432 mkwrite_device_info(dev_priv)->page_sizes = 1433 I915_GTT_PAGE_SIZE_4K; 1434 1435 dev_priv->mm.unordered_timeline = dma_fence_context_alloc(1); 1436 1437 intel_timelines_init(dev_priv); 1438 1439 ret = i915_gem_init_userptr(dev_priv); 1440 if (ret) 1441 return ret; 1442 1443 intel_uc_fetch_firmwares(&dev_priv->gt.uc); 1444 1445 ret = intel_wopcm_init(&dev_priv->wopcm); 1446 if (ret) 1447 goto err_uc_fw; 1448 1449 /* This is just a security blanket to placate dragons. 1450 * On some systems, we very sporadically observe that the first TLBs 1451 * used by the CS may be stale, despite us poking the TLB reset. If 1452 * we hold the forcewake during initialisation these problems 1453 * just magically go away. 1454 */ 1455 mutex_lock(&dev_priv->drm.struct_mutex); 1456 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL); 1457 1458 ret = i915_init_ggtt(dev_priv); 1459 if (ret) { 1460 GEM_BUG_ON(ret == -EIO); 1461 goto err_unlock; 1462 } 1463 1464 ret = i915_gem_init_scratch(dev_priv, 1465 IS_GEN(dev_priv, 2) ? SZ_256K : PAGE_SIZE); 1466 if (ret) { 1467 GEM_BUG_ON(ret == -EIO); 1468 goto err_ggtt; 1469 } 1470 1471 ret = intel_engines_setup(dev_priv); 1472 if (ret) { 1473 GEM_BUG_ON(ret == -EIO); 1474 goto err_unlock; 1475 } 1476 1477 ret = i915_gem_contexts_init(dev_priv); 1478 if (ret) { 1479 GEM_BUG_ON(ret == -EIO); 1480 goto err_scratch; 1481 } 1482 1483 ret = intel_engines_init(dev_priv); 1484 if (ret) { 1485 GEM_BUG_ON(ret == -EIO); 1486 goto err_context; 1487 } 1488 1489 intel_init_gt_powersave(dev_priv); 1490 1491 ret = intel_uc_init(&dev_priv->gt.uc); 1492 if (ret) 1493 goto err_pm; 1494 1495 ret = i915_gem_init_hw(dev_priv); 1496 if (ret) 1497 goto err_uc_init; 1498 1499 /* Only when the HW is re-initialised, can we replay the requests */ 1500 ret = intel_gt_resume(&dev_priv->gt); 1501 if (ret) 1502 goto err_init_hw; 1503 1504 /* 1505 * Despite its name intel_init_clock_gating applies both display 1506 * clock gating workarounds; GT mmio workarounds and the occasional 1507 * GT power context workaround. Worse, sometimes it includes a context 1508 * register workaround which we need to apply before we record the 1509 * default HW state for all contexts. 1510 * 1511 * FIXME: break up the workarounds and apply them at the right time! 1512 */ 1513 intel_init_clock_gating(dev_priv); 1514 1515 ret = intel_engines_verify_workarounds(dev_priv); 1516 if (ret) 1517 goto err_gt; 1518 1519 ret = __intel_engines_record_defaults(dev_priv); 1520 if (ret) 1521 goto err_gt; 1522 1523 if (i915_inject_probe_failure()) { 1524 ret = -ENODEV; 1525 goto err_gt; 1526 } 1527 1528 if (i915_inject_probe_failure()) { 1529 ret = -EIO; 1530 goto err_gt; 1531 } 1532 1533 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL); 1534 mutex_unlock(&dev_priv->drm.struct_mutex); 1535 1536 return 0; 1537 1538 /* 1539 * Unwinding is complicated by that we want to handle -EIO to mean 1540 * disable GPU submission but keep KMS alive. We want to mark the 1541 * HW as irrevisibly wedged, but keep enough state around that the 1542 * driver doesn't explode during runtime. 1543 */ 1544 err_gt: 1545 mutex_unlock(&dev_priv->drm.struct_mutex); 1546 1547 intel_gt_set_wedged(&dev_priv->gt); 1548 i915_gem_suspend(dev_priv); 1549 i915_gem_suspend_late(dev_priv); 1550 1551 i915_gem_drain_workqueue(dev_priv); 1552 1553 mutex_lock(&dev_priv->drm.struct_mutex); 1554 err_init_hw: 1555 intel_uc_fini_hw(&dev_priv->gt.uc); 1556 err_uc_init: 1557 intel_uc_fini(&dev_priv->gt.uc); 1558 err_pm: 1559 if (ret != -EIO) { 1560 intel_cleanup_gt_powersave(dev_priv); 1561 intel_engines_cleanup(dev_priv); 1562 } 1563 err_context: 1564 if (ret != -EIO) 1565 i915_gem_contexts_fini(dev_priv); 1566 err_scratch: 1567 i915_gem_fini_scratch(dev_priv); 1568 err_ggtt: 1569 err_unlock: 1570 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL); 1571 mutex_unlock(&dev_priv->drm.struct_mutex); 1572 1573 err_uc_fw: 1574 intel_uc_cleanup_firmwares(&dev_priv->gt.uc); 1575 1576 if (ret != -EIO) { 1577 i915_gem_cleanup_userptr(dev_priv); 1578 intel_timelines_fini(dev_priv); 1579 } 1580 1581 if (ret == -EIO) { 1582 mutex_lock(&dev_priv->drm.struct_mutex); 1583 1584 /* 1585 * Allow engine initialisation to fail by marking the GPU as 1586 * wedged. But we only want to do this where the GPU is angry, 1587 * for all other failure, such as an allocation failure, bail. 1588 */ 1589 if (!intel_gt_is_wedged(&dev_priv->gt)) { 1590 i915_probe_error(dev_priv, 1591 "Failed to initialize GPU, declaring it wedged!\n"); 1592 intel_gt_set_wedged(&dev_priv->gt); 1593 } 1594 1595 /* Minimal basic recovery for KMS */ 1596 ret = i915_ggtt_enable_hw(dev_priv); 1597 i915_gem_restore_gtt_mappings(dev_priv); 1598 i915_gem_restore_fences(dev_priv); 1599 intel_init_clock_gating(dev_priv); 1600 1601 mutex_unlock(&dev_priv->drm.struct_mutex); 1602 } 1603 1604 /* Flush any deferred RCU cleanup */ 1605 rcu_barrier(); > 1606 flush_workqueue(dev_priv->rq); 1607 1608 i915_gem_drain_freed_objects(dev_priv); 1609 return ret; 1610 } 1611 --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation
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