From: Michel Thierry <michel.thie...@intel.com>
Enable Small PL for power benefit.
Signed-off-by: Michel Thierry <michel.thie...@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demar...@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +++++
drivers/gpu/drm/i915/i915_reg.h | 3 +++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 347ba16346d3..f3367339f445 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1285,6 +1285,11 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
wa_write_or(wal,
GEN12_L3SQCREG2,
GEN12_LQSC_FLUSH_COHERENT_LINES);
+
+ /* Wa_1406941453:tgl */
+ wa_masked_en(wal,
+ SAMPLER_MODE,
+ SAMPLER_ENABLE_SMALL_PL);
}
if (IS_GEN(i915, 11)) {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d048c349e07e..712616fcd6b3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9009,6 +9009,9 @@ enum {
#define GEN9_DG_MIRROR_FIX_ENABLE (1 << 5)
#define GEN9_CCS_TLB_PREFETCH_ENABLE (1 << 3)
+#define SAMPLER_MODE _MMIO(0xe18c)
+#define SAMPLER_ENABLE_SMALL_PL (1 << 15)
+
#define GEN8_ROW_CHICKEN _MMIO(0xe4f0)
#define FLOW_CONTROL_ENABLE (1 << 15)
#define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1 << 8)
--
2.21.0
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