On Tue, Apr 09, 2013 at 03:25:37PM +0300, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrj...@linux.intel.com> > > IVB+ supports 32 fence registers, bump the maximum in the test.
Then again the test is only relevant for gen2/3 (and 1), and I don't forsee the use of fences for GPU surface tiling being resurrected. On the other hand, the test makes sure that future gpus ignore the old restrictions. One feature request for the test: feed in > max_fences expect ENOSPC/EDEADLCK on gen2/3. -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
