On Thu, Mar 28, 2013 at 09:27:31AM +0200, Jani Nikula wrote:
> On Wed, 27 Mar 2013, Jesse Barnes <jbar...@virtuousgeek.org> wrote:
> > From: Chris Wilson <ch...@chris-wilson.co.uk>
> >
> > Modifying the clock sources (via the DREF control on the PCH) is a slow
> > multi-stage process as we need to let the clocks stabilise between each
> > stage. If we are not actually changing the clock sources, then we can
> > return early.
> >
> > Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 83
> > +++++++++++++++++++++++++---------
> > 1 file changed, 61 insertions(+), 22 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 8f0db8c..9d05b30 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -4833,7 +4833,7 @@ static void ironlake_init_pch_refclk(struct
> > drm_device *dev)
> > struct drm_i915_private *dev_priv = dev->dev_private;
> > struct drm_mode_config *mode_config = &dev->mode_config;
> > struct intel_encoder *encoder;
> > - u32 temp;
> > + u32 val, final;
> > bool has_lvds = false;
> > bool has_cpu_edp = false;
> > bool has_pch_edp = false;
> > @@ -4876,70 +4876,109 @@ static void ironlake_init_pch_refclk(struct
> > drm_device *dev)
> > * PCH B stepping, previous chipset stepping should be
> > * ignoring this setting.
> > */
> > - temp = I915_READ(PCH_DREF_CONTROL);
> > + val = I915_READ(PCH_DREF_CONTROL);
> > +
> > + /* As we must carefully and slowly disable/enable each source in turn,
> > + * compute the final state we want first and check if we need to
> > + * make any changes at all.
> > + */
> > + final = val;
> > + final &= ~DREF_NONSPREAD_SOURCE_MASK;
> > + if (has_ck505)
> > + final |= DREF_NONSPREAD_CK505_ENABLE;
> > + else
> > + final |= DREF_NONSPREAD_SOURCE_ENABLE;
> > +
> > + final &= ~DREF_SSC_SOURCE_MASK;
> > + final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
> > + final &= ~DREF_SSC1_ENABLE;
> > +
> > + if (has_panel) {
> > + final |= DREF_SSC_SOURCE_ENABLE;
> > +
> > + if (intel_panel_use_ssc(dev_priv) && can_ssc)
> > + final |= DREF_SSC1_ENABLE;
> > +
> > + if (has_cpu_edp) {
> > + if (intel_panel_use_ssc(dev_priv) && can_ssc)
> > + final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
> > + else
> > + final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
> > + } else
> > + final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
>
> I've been assimilated, I dislike not having braces in all branches if
> one branch requires them... but that's bikeshedding. On the stuff that
> matters,
I've punted on this bikeshed (checkpatch didn't yell), but fixed another
one ;-)
>
> Reviewed-by: Jani Nikula <jani.nik...@intel.com>
I've figured that speeding this up and moving it into
->global_modeset_resources are rather orthogonal, since even with fastboot
we might want to adjust pm state a bit (e.g. with the power wells stuff).
So even when this is move into the modeset code and thought more clever
tricks, we'll still run it in the boot-up modeset path.
Queued for -next, thanks for the patch.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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